LAN9730 Datasheet, PDF (98/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
TABLE 4-62: EEPROM EXAMPLE - 256 BYTE EEPROM (CONTINUED)
EEPROM
Address
8Fh
90h
91h
92h
93h
94h - FFh
EEPROM Contents
(Hex)
03
FF
00
FF
00
-
Description
Number of Endpoints used for this interface (Less Endpoint 0)
Class Code
Subclass Code
Protocol Code
Index of String Descriptor Describing this interface
Data storage for use by host as desired
4.8 Customized Operation Without EEPROM
The device provides the capability to customize operation without the use of an EEPROM. Descriptor information and
initialization quantities normally fetched from EEPROM and used to initialize descriptors and elements of the System
Control and Status Registers may be specified via an alternate mechanism. This alternate mechanism involves the use
of the Descriptor RAM in conjunction with the Attributes registers and select elements of the System Control and Status
Registers. The software device driver orchestrates the process by performing the following actions in the order indi-
cated:
• Initialization of SCSR Elements in Lieu of EEPROM Load
• Attribute Register Initialization
• Descriptor RAM Initialization
• Enable Descriptor RAM and Flag Attribute Registers as Source
• Inhibit Reset of Select SCSR Elements
The following subsections explain these actions. The Attributes registers must be written prior to initializing the Descrip-
tor RAM. Failure to do this will prevent the RMT_WKUP flag from being overwritten by the bmAttributes of the Config-
uration Descriptor.
4.8.1 INITIALIZATION OF SCSR ELEMENTS IN LIEU OF EEPROM LOAD
During EEPROM operation, the following register fields are initialized by the hardware using the values contained in the
EEPROM. In the absence of an EEPROM, the software device driver must initialize these quantities:
• MAC Address High Register (ADDRH) and MAC Address Low Register (ADDRL)
• LED Select (LED_SEL) bit of the LED General Purpose IO Configuration Register (LED_GPIO_CFG)
• GPIO Wake 0-10 (GPIOWKn) field of the General Purpose IO Wake Enable and Polarity Register (GPIO_WAKE)
4.8.2 ATTRIBUTE REGISTER INITIALIZATION
The Attributes registers are as follows:
• HS Descriptor Attributes Register (HS_ATTR)
• FS Descriptor Attributes Register (FS_ATTR)
• String Descriptor Attributes Register 0 (STRNG_ATTR0)
• String Descriptor Attributes Register 1 (STRNG_ATTR1)
• Flag Attributes Register (FLAG_ATTR)
All of these registers, with the exception of FLAG_ATTR, contain fields defining the lengths of the descriptors written
into the Descriptor RAM. If the descriptor is not written into the Descriptor RAM, the associated entry in the Attributes
register must be written as 0. Writing an erroneous or illegal length will result in untoward operation and unexpected
results.
The Flag Attributes Register (FLAG_ATTR) provides the mechanism to initialize components of the Configuration Flags
and GPIO PME Flags that are stand-alone and not part of any other System Control and Status Register. During
EEPROM operation, the analogous fields in this register are read by the hardware from the EEPROM and are not avail-
able to the software for read-back or modification.
Note: The software device driver must initialize these registers prior to initializing the Descriptor RAM.
DS00001946A-page 98
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