LAN9730 Datasheet, PDF (119/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
6.0 REGISTER DESCRIPTIONS
6.1 Register Nomenclature
Table 6-1 describes the register bit attributes used throughout this document.
TABLE 6-1: REGISTER BIT TYPES
Register Bit Type Notation
Register Bit Description
R
Read: A register or bit with this attribute can be read.
W
Write: A register or bit with this attribute can be written.
RO
Read only: Read only. Writes have no effect.
RS
Read to Set: This bit is set on read.
WO
Write only: If a register or bit is write-only, reads will return unspecified data.
WC
Write One to Clear: Writing a one clears the value. Writing a zero has no effect.
WAC
Write Anything to Clear: Writing anything clears the value.
RC
Read to Clear: Contents is cleared after the read. Writes have no effect.
LL
Latch Low: Clear on read of register.
LH
Latch High: Clear on read of register.
SC
Self-Clearing: Contents is self-cleared after the being set. Writes of zero have no
effect. Contents can be read.
RO/LH
NASR
Read Only, Latch High: This mode is used by the Ethernet PHY registers. Bits with
this attribute will stay high until the bit is read. After a read, the bit will remain high, but
will change to low if the condition that caused the bit to go high is removed. If the bit has
not been read, the bit will remain high regardless of if its cause has been removed.
Not Affected by Software Reset. The state of NASR bits does not change on asser-
tion of a software reset.
RESERVED
Reserved Field: Reserved fields must be written with zeros, unless otherwise indi-
cated, to ensure future compatibility. The value of reserved bits is not guaranteed on a
read.
6.2 Register Memory Map
TABLE 6-2: REGISTER MEMORY MAP
Address
000h - 0FFh
100h - 1FCh
Symbol
SCSR
MCSR
Register Name
System Control and Status Registers
MAC Control and Status Registers
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DS00001946A-page 119