LAN9730 Datasheet, PDF (106/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
4.12.1 DETECTING WAKEUP EVENTS
The following sections illustrate and discuss the wakeup detection logic.
4.12.1.1 Wake Detection Logic
A simplified diagram of the wake event detection logic is shown in Figure 4-30.
FIGURE 4-30:
WAKE EVENT DETECTION BLOCK DIAGRAM
WU detect
WUEN
(WUSCR Register)
RW
GUEN
(WUSCR Register)
RW
GU detect
MPEN
(WUSCR Register)
RW
MP detect
PFDA_EN
(WUSCR Register)
RW
PFDA detect
BCAST_EN
(WUSCR Register)
RW
BCast detect
WUFR
(WUSCR Register)
MPR
(WUSCR Register)
PFDA_FR
(WUSCR Register)
Good Frame
Received
BCAST_FR
(WUCSR Register)
SUSPEND0
SUSPEND1
SUSPEND2
SUSPEND3
WOL_EN
(PMT_CTL Register)
RW
WUPS[1]
(PMT_CTL Register)
ED_EN
(PMT_CTL Register)
RW
WUPS[0]
(PMT_CTL Register)
remote_wake
GPIO0_DET
.
.
.
GPIO10_DET
Note: Diagram does not represent actual hardware implementation.
The functionality of GPIOs 0-6 and GPIOs 8-10 is slightly different. The functionality of GPIO7 is similar to that of GPIOs
0-6, with the additional requirement that it must cause a wakeup event when enabled for use in PHY Link Up detection.
Note: GPIOs 0-7 are only available for use during internal Ethernet PHY mode of operation. The functionality of
GPIOs 0-6 is depicted in Figure 4-31, while that of GPIO7 is shown in Figure 4-32.
GPIOs 8-10 are available for use in both internal and external Ethernet PHY mode of operation. Their functionality is
depicted in Figure 4-33.
DS00001946A-page 106
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