LAN9730 Datasheet, PDF (155/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
6.3.25 TRANSMIT FIFO LEVEL DEBUG REGISTER (DBG_TX_FIFO_LVL)
Address:
078h
Size:
32 bits
Bits
31:28
27:16
Description
RESERVED
TX FIFO Read Level (TXRDLVL)
This is a DWORD count defined as follows:
The count is increased by the number of DWORDs contained in the packet
after the ENTIRE packet has been written into the FIFO.
15:12
11:0
As a packet is read from the FIFO, it is decremented each time a DWORD is
read.
Note: Rewinds are not supported.
RESERVED
TX FIFO Write Level (TXWRLVL)
This is a DWORD count defined as follows:
As a packet is written into the FIFO, it is incremented each time a DWORD is
written.
Whenever a COMPLETE packet has been read from the FIFO, it is decreased
by the number of DWORDs contained in the packet.
On rewind, it is decreased by the number of DWORDs of the packet that has
currently been transferred into the FIFO.
Note:
Write side rewinds are supported, i.e., if a USB packet is received
with an error, the packet is rewound out and re-received from the
host.
Type
RO
RO
RO
RO
Default
-
000h
-
000h
 2012-2015 Microchip Technology Inc.
DS00001946A-page 155