LAN9730 Datasheet, PDF (7/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
1.2.1 OVERVIEW
The LAN9730/LAN9730i is a high performance solution for USB to 10/100 Ethernet port bridging. With applications
ranging from embedded systems, set-top boxes, and PVRs, to USB port replicators, and test instrumentation, the device
is targeted as a high-performance, low-cost USB/Ethernet connectivity solution.
The LAN9730/LAN9730i contains an integrated 10/100 Ethernet PHY, HSIC interface, Hi-Speed USB 2.0 device con-
troller, 10/100 Ethernet MAC, TAP controller, EEPROM controller, and a FIFO controller with a total of 30 kB of internal
packet buffering. Two kB of buffer memory are allocated to the Transaction Layer Interface (TLI), while 28 kB are allo-
cated to the FIFO Controller (FCT).
The internal USB 2.0 device controller is compliant with the USB 2.0 Hi-Speed standard. The HSIC interface is compliant
with the High-Speed Interchip USB Electrical Specification Revision 1.0. High-Speed Inter-Chip (HSIC) is a digital inter-
connect bus that enables the use of USB technology as a low-power chip-to-chip interconnect at speeds up to 480 Mb/
s. The device implements Control, Interrupt, Bulk-In and Bulk-Out USB Endpoints.
The Ethernet controller supports auto-negotiation, auto-polarity correction, HP Auto-MDIX, and is compliant with the
IEEE 802.3 and 802.3u standards. An external MII interface provides support for an external Fast Ethernet PHY, Home-
PNA, and HomePlug functionality.
Multiple power management features are provided, including various low-power modes, and Magic Packet, Wake On
LAN and Link Status Change wake events. These wake events can be programmed to initiate a USB remote wakeup.
A PCI-like PME wake is also supported when the host controller is disabled.
An internal EEPROM controller exists to load various USB configuration information and the device MAC address. The
integrated IEEE 1149.1 compliant TAP controller provides boundary scan via JTAG.
1.2.2 USB
The USB portion of the LAN9730/LAN9730i consists of the USB Device Controller (UDC), USB Bulk-Out Packet
Receiver (URX), USB Bulk-In Packet Transmitter (UTX), Control Block (CTL), System Control and Status Registers
(SCSR), and HSIC interface.
The USB device controller (UDC) contains a USB low-level protocol interpreter which implements the USB bus protocol,
packet generation/extraction, PID/Device ID parsing, and CRC coding/decoding with autonomous error handling. It has
autonomous protocol handling functions such as stall condition clearing on setup packets, suspend/resume/reset con-
ditions, and remote wakeup. It also autonomously handles contingency operations for error conditions such as retry for
CRC errors, Data toggle errors, and generation of NYET, STALL, ACK, and NACK depending on the Endpoint buffer
status. The UDC implements four USB Endpoints: Control, Interrupt, Bulk-In, and Bulk-Out.
The Control block (CTL) manages traffic to/from the control Endpoint that is not handled by the UDC and constructs the
packets used by the interrupt Endpoint. The CTL is responsible for handling some USB standard commands and all
vendor specific commands. The vendor specific commands allow for efficient statistics collection and access to the
SCSR.
The URX and UTX implement the Bulk-Out and Bulk-In pipes, respectively, which connect the USB host and the UDC.
They perform the following functions:
The URX passes USB Bulk-Out packets to the FIFO Controller (FCT). It tracks whether or not a USB packet is errone-
ous. It instructs the FCT to flush erroneous packets by rewinding its write pointer.
The UTX retrieves Ethernet frames from the FCT and constructs USB Bulk-In packets from them. If the handshake for
a transmitted Bulk-In packet does not complete, the UTX is capable of retransmitting the packet. The UTX will not
instruct the FCT to advance its read head pointer until the current USB packet has been successfully transmitted to the
USB host.
Both the URX and UTX are responsible for handling Ethernet frames encapsulated over USB by one of the following
methods:
• Multiple Ethernet frames per USB Bulk packet
• Single Ethernet frame per USB Bulk packet
The UDC also implements the System Control and Status Register (SCSR) space used by the host to obtain status and
control overall system operation.
The integrated HSIC interface is compliant with the High-Speed Interchip USB Electrical Specification Revision 1.0 (09-
23-07) and supports the Hi-Speed mode of operation.
 2012-2015 Microchip Technology Inc.
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