LAN9730 Datasheet, PDF (31/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
Note: When using SEF mode, there will never be any unused bytes added for end alignment padding. The USB
transfer always ends on the last byte of the Ethernet frame.
Note: When RX COE is enabled, the last byte would pertain to the RX COE Word.
Once a decision is made to end a transfer and a short packet or ZLP has been sent, it is possible that an Ethernet frame
will arrive prior to the UTX seeing an ACK from the host for the previous Bulk-In packet. In this case, the UTX must
continue to repeat the short packet or ZLP until the ACK is received for the end of the previous transfer. The UTX must
not start a new transfer, or re-use the previous data toggle, to begin sending the next Ethernet frame until the ACK has
been received for the end of the previous transfer.
In order to more efficiently utilize USB bandwidth in MEF mode, the UTX has a mechanism for delaying the transmission
of a short packet, or ZLP. This mode entails having the UTX wait a time defined by the Bulk-In Delay Register
(BULK_IN_DLY) before terminating the burst. A value of zero in this register disables this feature. By default, a delay of
34 µs is used.
After the UTX transmits the last USB wPacketSize packet in a burst, the UTX will enable an internal timer. When the
Bulk-In Delay time expires, any Bulk-In data will be transmitted upon reception of the next Bulk-In Token. If enough data
arrives before the timer elapses to build at least one maximum sized packet, then the UTX will transmit this packet when
it receives the next Bulk-In Token. After packet transmission, the UTX will then reset its internal timer and delay the short
packet, or ZLP, transmission until the Bulk-In Delay time elapses.
In the case where the FIFO is empty and a single Ethernet packet less than the USB wPacketSize has been received,
the UTX will enable its internal timer. If enough data arrives before the timer elapses to build at least one maximum sized
packet, then the UTX will transmit this packet when it receives the next Bulk-In Token and will reset the internal timer.
Otherwise, the short packet, or ZLP, is sent in response to the first Bulk-In Token received after the timer expires.
The UTX will NACK any Bulk-In tokens while waiting for the Bulk-In Delay to elapse. This NACK response is not affected
by the Bulk-In Empty Response (BIR). The Bulk-In Empty Response (BIR) setting only applies after the Bulk-In Delay
time expires.
The UTX, via the Burst Cap Register (BURST_CAP), is capable or prematurely terminating a burst. When the amount
transmitted exceeds the value specified in this register, the UTX transmits a ZLP after the current Bulk-In packet com-
pletes. The Burst Cap Register (BURST_CAP) uses units of USB packet size (512 bytes). To enable use of the Burst
Cap register, the Burst Cap Enable (BCE) bit in the Hardware Configuration Register (HW_CFG) must be set. For proper
operation, the BURST_CAP field should be set to a value greater than 4. Burst Cap enforcement is disabled if BURST_-
CAP is set to a value less than or equal to 4.
Whenever Burst Cap enforcement is disabled, the UTX will respond with a ZLP (when Bulk-In Empty Response (BIR)
=0) or with NACK (when Bulk-In Empty Response (BIR) = 1).
Whenever Burst Cap enforcement is enabled (BURST_CAP value is legal), the following holds:
• Let BURST = BURST_CAP * 512
The burst may terminate at BURST-4, BURST-3, BURST-2, BURST-1, or BURST bytes, or, when the RX FIFO
runs out of data. The burst is terminated with either a short USB packet or with a ZLP.
Note: Ethernet frames are not fragmented across bursts when using Burst Cap enforcement.
In the case of an error condition, the UTX will issue a rewind to the FCT. This occurs when the UTX completes trans-
mitting a Bulk-In packet and does not receive an ACK from the host. In this case, the next frame received by the UTX
will be another In token and the Bulk-In packet is retransmitted. When the ACK is finally received, the UTX notifies the
FCT. The FCT will then advance the read head pointer to the next packet.
Note: The UTX will never stall the Endpoint. The Endpoint can only be stalled by the host.
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DS00001946A-page 31