LAN9730 Datasheet, PDF (176/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
6.4.11 WAKEUP FRAME FILTER (WUFF)
Address:
128h
Size:
32 bits
This register is used to configure the Wakeup Frame Filter.
Bits
Description
31:0 Wakeup Frame Filter (WFF)
The Wakeup Frame Filter is configured through this register using an indexing
mechanism. Following a reset, the MAC loads the first value written to this
location to the first DWORD in the Wakeup Frame Filter (Filter 0 Byte Mask 0).
The second value written to this location is loaded to the second DWORD in
the Wakeup Frame Filter (Filter 0 Byte Mask 1) and so on. Once 40 DWORDs
(8 filters) have been written, the internal pointer will once again point to the
first entry and the filter entries can be modified in the same manner. Similarly,
40 DWORDS (8 filters) can be read sequentially to obtain the values stored in
the WFF. Refer to Section 4.5.5, "Wakeup Frame Detection" for further infor-
mation concerning the Wakeup Frame Filter.
Note:
This register should be read and written using 40 (8 filters)
consecutive DWORD operations. Failure to read or write the entire
contents of the WFF may cause the internal read/write pointers to
be left in a position other than pointing to the first entry. A
mechanism for resetting the internal pointers to the beginning of the
WFF is available via the WFF Pointer Reset (WFF_PTR_RST) bit
of the Wakeup Control and Status Register (WUCSR). This
mechanism enables the application program to re-synchronize with
the internal WFF pointers if it has not previously read/written the
complete contents of the WFF.
Type
R/W
Default
0000_0000h
DS00001946A-page 176
 2012-2015 Microchip Technology Inc.