LAN9730 Datasheet, PDF (122/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
6.3.2 INTERRUPT STATUS REGISTER (INT_STS)
Address:
008h
Size:
32 bits
Bits
Description
Type
31:19
18
17
RESERVED
MAC Reset Time Out (MACRTO_INT)
This interrupt signifies that the 8 ms reset watchdog timer has timed out. This
means that the Ethernet PHY is not supplying the rx_clk or tx_clk. After the
timer times out, the MAC reset is deasserted asynchronously.
TX Stopped (TXSTOP_INT)
This interrupt is asserted when the Stop Transmitter (STOP_TX) bit in Trans-
mit Configuration Register (TX_CFG) is set and the transmitter is halted.
RO
R/WC
R/WC
Note: The source of this interrupt is a pulse.
16 RX Stopped (RXSTOP_INT)
This interrupt is issued when the receiver is halted.
R/WC
Note: The source of this interrupt is a pulse.
15 PHY Interrupt (PHY_INT)
RO
Indicates a PHY Interrupt event.
Note: Depending on configuration, this may report the interrupt status of
the internal or the external PHY.
Note: The source of this interrupt is a level. The interrupt persists until it
is cleared in the PHY.
14 Transmitter Error (TXE)
When generated, indicates that the transmitter has encountered an error.
Refer to Section 4.4.2.5, "TX Error Detection" for a description of the condi-
tions that will cause a TXE.
R/WC
Note: The source of this interrupt is a pulse.
13 TX Data FIFO Underrun Interrupt (TDFU)
Generated when the TX Data FIFO underruns.
R/WC
Note: The source of this interrupt is a pulse.
12 TX Data FIFO Overrun Interrupt (TDFO)
Generated when the TX Data FIFO is full, and another write is attempted.
R/WC
Note: This interrupt should never occur and indicates a catastrophic
hardware error.
Note: The source of this interrupt is a pulse.
11 RX Dropped Frame Interrupt (RXDF_INT)
This interrupt is issued whenever a receive frame is dropped.
R/WC
Note: The source of this interrupt is a pulse.
10:0 GPIO [10:0] (GPIOx_INT)
Interrupts are generated from the GPIOs. These interrupts are configured
through the GPIO_CFG and LED_GPIO_CFG registers.
R/WC
Note 6-3
Note: The sources for these interrupts are a level.
Note 6-2
Note 6-3
The default depends on the state of the GPIO pin.
The clearing of a GPIOx_INT bit also clears the corresponding GPIO wake event.
Default
-
0b
0b
0b
-
0b
0b
0b
0b
Note 6-2
DS00001946A-page 122
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