LAN9730 Datasheet, PDF (203/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
7.5.3 POWER-ON CONFIGURATION STRAP VALID TIMING
Figure 7-3 illustrates the configuration strap valid timing requirement in relation to power-on. In order for valid configu-
ration strap values to be read at power-on, the following timing requirements must be met.
FIGURE 7-3:
POWER-ON CONFIGURATION STRAP VALID TIMING
VDD33IO
Configuration Straps
2.0 V
t_cfg
TABLE 7-15: POWER-ON CONFIGURATION STRAP VALID TIMING
Symbol
t_cfg
Description
Configuration strap valid time
Min.
Typ.
Max.
Unit
15
ms
7.5.4 RESET AND CONFIGURATION STRAP TIMING
Figure 7-4 illustrates the nRESET pin timing requirements and its relation to the configuration strap pins and output
drive. Assertion of nRESET is not a requirement. However, if used, it must be asserted for the minimum period specified.
FIGURE 7-4:
nRESET RESET PIN TIMING
nRESET
Configuration
Strap Pins
Output Drive
t_rstia
t_css
t_csh
t_odad
TABLE 7-16: nRESET RESET PIN TIMING VALUES
Symbol
Description
Min.
Typ.
Max.
Unit
t_rstia
nRESET input assertion time
1
µs
t_css
Configuration strap pins setup to nRESET deassertion
200
ns
t_csh
Configuration strap pins hold after nRESET deassertion
10
ns
t_odad
Output drive after nRESET deassertion
30
ns
 2012-2015 Microchip Technology Inc.
DS00001946A-page 203