LAN9730 Datasheet, PDF (205/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
7.5.6 MII INTERFACE TIMING
This section specifies the MII interface transmit and receive timing.
Note: The MII timing adheres to the IEEE 802.3 specification. Refer to the IEEE 802.3 specification for additional
MII timing information.
FIGURE 7-6:
MII TRANSMIT TIMING
TXCLK
(INPUT)
TXD[3:0]
(OUTPUT)
TXEN, TXER
(OUTPUT)
t_clkp
t_clkh t_clkl
t_val
t_val
t_invld
t_invld
t_val
TABLE 7-18: MII TRANSMIT TIMING VALUES
Symbol
t_clkp
t_clkh
t_clkl
t_val
t_invld
Description
TXCLK period
TXCLK high time
TXCLK low time
TXD[3:0], TXEN, TXER output valid from rising
edge of TXCLK
TXD[3:0], TXEN, TXER output invalid from ris-
ing edge of TXCLK
Min
40
t_clkp*0.4
t_clkp*0.4
0
Max
t_clkp*0.6
t_clkp*0.6
22.0
Units
ns
ns
ns
ns
Notes
Note 7-11
ns
Note 7-11
Note 7-11 Timing was designed for a system load between 10 pf and 25 pf.
 2012-2015 Microchip Technology Inc.
DS00001946A-page 205