LAN9730 Datasheet, PDF (15/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
TABLE 2-1: MII INTERFACE PINS (CONTINUED)
Num Pins
Name
1
Transmit Data
3
(Internal PHY
Mode)
Symbol
TXD3
Buffer
Type
IS/O8
(PU)
Transmit Data
3
(External
PHY Mode)
General Pur-
pose I/O 7
(Internal PHY
Mode Only)
TXD3
GPIO7
O8
(PU)
IS/O8/
OD8
(PU)
HSIC Output
Impedance
Configuration
Strap
50DRIVER_EN
IS
(PU)
Description
In Internal PHY Mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 125 for additional information.
In External PHY Mode, this pin functions as the
transmit data 3 output to the external PHY.
This General Purpose I/O pin is fully programma-
ble as either a push-pull output, an open-drain
output or a Schmitt-triggered input.
Note:
GPIO7 may provide additional external
PHY Link Up related functionality. Refer
to Section 4.12.2.4, "Enabling External
PHY Link Up Wake Events" for
additional information.
The 50DRIVER_EN strap selects the driver out-
put impedance for the HSIC_DATA and
HSIC_STROBE pins.
0 = 40 Ω output impedance
1 = 50 Ω output impedance
See Note 2-1 for more information on configura-
tion straps.
 2012-2015 Microchip Technology Inc.
DS00001946A-page 15