LAN9730 Datasheet, PDF (91/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
4.7.4.1 Supported EEPROM Operations
The EEPROM controller supports the following EEPROM operations under host control via the E2P_CMD register. The
operations are commonly supported by “93C46” EEPROM devices. A description and functional timing diagram is pro-
vided below for each operation. Refer to the E2P_CMD register description in Section 6.3.12, "EEPROM Command
Register (E2P_CMD)" for E2P_CMD field settings for each command.
ERASE (Erase Location): If erase/write operations are enabled in the EEPROM, this command will erase the location
selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the EEPROM does not respond within 30 ms.
FIGURE 4-21:
EEPROM ERASE CYCLE
tCSL
EECS
EECLK
EEDIO (OUTPUT)
1
1
1
A6
A0
EEDIO (INPUT)
ERASE CYCLE
ERAL (Erase All): If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the
entire EEPROM. The EPC_TO bit is set if the EEPROM does not respond within 30 ms.
FIGURE 4-22:
EEPROM ERAL CYCLE
tCSL
EECS
EECLK
EEDIO (OUTPUT)
1
0
0
1
0
EEDIO (INPUT)
ERAL CYCLE
 2012-2015 Microchip Technology Inc.
DS00001946A-page 91