LAN9730 Datasheet, PDF (120/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
6.3 System Control and Status Registers
TABLE 6-3: DEVICE CONTROL AND STATUS REGISTER MAP
Address
Symbol
000h
ID_REV
004h
008h
00Ch
010h
014h
RESERVED
INT_STS
RX_CFG
TX_CFG
HW_CFG
018h
RX_FIFO_INF
01Ch TX_FIFO_INF
020h
PMT_CTL
024h
LED_GPIO_CFG
028h
02Ch
030h
034h
038h
GPIO_CFG
AFC_CFG
E2P_CMD
E2P_DATA
BURST_CAP
03Ch
RESERVED
040h
DP_SEL
044h
DP_CMD
048h
DP_ADDR
04Ch
050h
054h – 060h
064h
068h
DP_DATA0
DP_DATA1
RESERVED
GPIO_WAKE
INT_EP_CTL
06Ch BULK_IN_DLY
070h
DBG_RX_FIFO_LVL
074h
DBG_RX_FIFO_PTR
078h
DBG_TX_FIFO_LVL
07Ch
DBG_TX_FIFO_PTR
080h – 09Fh RESERVED
0A0h
HS_ATTR
0A4h
FS_ATTR
0A8h
STRNG_ATTR0
0ACh STRNG_ATTR1
0B0h
FLAG_ATTR
0B4h – 0FFh RESERVED
Register Name
Device ID and Revision Register
Reserved for future expansion
Interrupt Status Register
Receive Configuration Register
Transmit Configuration Register
Hardware Configuration Register
Receive FIFO Information Register
Transmit FIFO Information Register
Power Management Control Register
LED General Purpose IO Configuration Register
General Purpose IO Configuration Register
Automatic Flow Control Configuration Register
EEPROM Command Register
EEPROM Data Register
Burst Cap Register
Reserved for future expansion
Data Port Select Register
Data Port Command Register
Data Port Address Register
Data Port Data 0 Register
Data Port Data 1 Register
Reserved for future expansion
General Purpose IO Wake Enable and Polarity Register
Interrupt Endpoint Control Register
Bulk-In Delay Register
Receive FIFO Level Debug Register
Receive FIFO Pointer Debug Register
Transmit FIFO Level Debug Register
Transmit FIFO Pointer Debug Register
Reserved for future expansion
HS Descriptor Attributes Register
FS Descriptor Attributes Register
String Descriptor Attributes Register 0
String Descriptor Attributes Register 1
Flag Attributes Register
Reserved for future expansion
DS00001946A-page 120
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