LAN9730 Datasheet, PDF (89/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
TABLE 4-58: GPIO PME FLAGS (CONTINUED)
Bits
Description
1 GPIO10 Detection Select
This bit selects the detection mode for GPIO10 when operating in PME mode. In PME mode, GPIO10 is
usable in both Internal and External PHY mode as a wakeup pin. This parameter defines whether the
wakeup should occur on an active high or active low signal.
0 = Active-low detection for GPIO10
1 = Active-high detection for GPIO10
Note: If GPIO PME Enable is 0, this bit is ignored.
0 RESERVED
4.7.2 EEPROM DEFAULTS
The signature value of 0xA5 is stored at address 0. A different signature value indicates to the EEPROM controller that
no EEPROM or an un-programmed EEPROM is attached to the device. In this case, the hardware default values are
used, as shown in Table 4-59. Refer to Section 4.3.1.6, "USB Descriptors" for further information about the default USB
values.
TABLE 4-59: EEPROM DEFAULTS
Field
MAC Address
Full-Speed Polling Interval (ms)
Hi-Speed Polling Interval (ms)
Configuration Flags
Maximum Power (mA)
Vendor ID
Product ID
Default Value
FFFFFFFFFFFFh
01h
04h
04h
FAh
0424h
9730h
Note: The Configuration Flags are affected by the RMT_WKP strap.
4.7.3 EEPROM AUTO-LOAD
Certain system level resets (USB reset, POR, nRESET, and SRST) cause the EEPROM contents to be loaded into the
device. After a reset, the EEPROM controller attempts to read the first byte of data from the EEPROM. If the value 0xA5
is read from the first address, then the EEPROM controller will assume that an external serial EEPROM is present.
Note: The USB reset only loads the MAC address.
The EEPROM controller will then load the entire contents of the EEPROM into an internal 512 byte SRAM. The contents
of the SRAM are accessed by the CTL (USB Control Block) as needed (i.e., to fill Get Descriptor commands). A detailed
explanation of the EEPROM byte ordering with respect to the MAC address is given in Section 6.4.3, "MAC Address
Low Register (ADDRL)".
If an 0xA5h is not read from the first address, the EEPROM controller will end initialization. The default values, as spec-
ified in Table 4-59, will then be assumed by the associated registers. It is then the responsibility of the host LAN driver
software to set the IEEE address by writing to the MAC’s ADDRH and ADDRL registers.
The device may not respond to the USB host until the EEPROM loading sequence has completed. Therefore, after
reset, the USB PHY is kept in the disconnect state until the EEPROM load has completed.
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DS00001946A-page 89