LAN9730 Datasheet, PDF (131/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
Bits
Description
4 PHY Reset (PHY_RST)
Writing a '1' to this bit resets the PHY. The internal logic automatically holds
the PHY reset for a minimum of 2 ms. When the PHY is released from reset,
this bit is automatically cleared. All writes to this bit are ignored while this bit is
high.
Note: The device will NAK all USB transfers until the PHY reset
completes.
3 Wake On LAN Enable (WOL_EN)
Enables WOL as a wakeup event.
Type
SC
R/W
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Enables (RES_CLR_WKP_EN) is set.
2 Energy-Detect Enable (ED_EN)
R/W
Enables Energy-Detect as a wakeup event.
This bit is automatically cleared at the completion of a resume sequence if
Resume Clears Remote Wakeup Enables (RES_CLR_WKP_EN) is set.
1:0 Wakeup Status (WUPS)
R/WC
This field indicates the cause of the current wakeup event. The WUPS[0] and
WUPS[1] bits are set and cleared independently. A WUPS bit may be cleared
by writing a ‘1’ to the corresponding bit. The encoding of these bits (WUPS[1],
WUPS[0]) is as follows:
WUPS[1:0]
00
X1
1X
Event
No wake-up event detected
Energy-Detect (SUSPEND1)
Wake On LAN (SUSPEND0) / Good Frame (SUSPEND3)
More than one bit may be set indicating that multiple events occurred.
The WUPS field will not be set unless the corresponding event is enabled
prior to entering the reduced power state.
These bits will set regardless of the values in Wake On LAN Enable
(WOL_EN) and Energy-Detect Enable (ED_EN).
If the Resume Clears Remote Wakeup Status (RES_CLR_WKP_STS) bit is
set, WUPS[1] will clear upon completion of a resume. See the Resume Clears
Remote Wakeup Status (RES_CLR_WKP_STS) bit for further details.
Note: It is not valid to simultaneously clear the WUPS bits and change the
contents of the Suspend Mode (SUSPEND_MODE) field.
Default
0b
0b
0b
00b
 2012-2015 Microchip Technology Inc.
DS00001946A-page 131