LAN9730 Datasheet, PDF (60/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
FIGURE 4-8:
TX EXAMPLE 3
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TX Command B
TX Command A
USB Packet 0
115 Byte
Ethernet
Frame
17 Byte Payload
TX Command B
TX Command A
15 Byte Payload
TX Command B
TX Command A
79 Byte Payload
TX Command B
TX Command A
Checksum Preamble
TX Command B
TX Command A
TX Command A
Data Start Offset = 2
First Segment = 0
Last Segment = 1
Buffer Size = 17
TX Command A
Data Start Offset = 0
First Segment = 0
Last Segment = 0
Buffer Size = 15
TX Command B
Frame Length = 111
TX Checksum Enable = 1
TX Command B
Frame Length = 111
TX Checksum Enable = 1
TX Command A
Data Start Offset = 3
First Segment = 0
Last Segment = 0
Buffer Size = 79
TX Command A
Data Start Offset = 0
First Segment = 1
Last Segment = 0
Buffer Size = 4
TX Command B
Frame Length = 111
TX Checksum Enable = 1
TX Command B
Frame Length = 111
TX Checksum Enable = 1
Checksum Preamble
TX Checksum Location = 50
TX Checksum Start Pointer = 14
4.4.2.10 Flushing the TX FIFO
The device allows for the host to flush the entire contents of the FCT TX FIFO. When a flush is activated, the read and
write pointers for the TX FIFO are returned to their reset state.
Before flushing the TX FIFO, the device’s transmitter must be stopped, as specified in Section 4.4.2.11. Once the trans-
mitter stop completion is confirmed, the Transmit FIFO Flush bit can be set in the Transmit Configuration Register
(TX_CFG) on page 124. This bit is cleared after the flush is complete.
DS00001946A-page 60
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