LAN9730 Datasheet, PDF (5/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
1.0 INTRODUCTION
1.1 General Terms
Byte
CSR
DWORD
FCT
FIFO
Frame
FSM
GPIO
HSIC
Host
Level-Triggered Sticky Bit
LFSR
MAC
MII
N/A
Packet
POR
RESERVED
SCSR
SMI
TLI
URX
UTX
WORD
ZLP
8 bits
Control and Status Registers
32 bits
FIFO Controller
First In First Out buffer
In the context of this document, a frame refers to transfers on the Ethernet
interface.
Finite State Machine
General Purpose I/O
High-Speed Inter-Chip
External system (includes processor, application software, etc.)
This type of status bit is set whenever the condition that it represents is
asserted. The bit remains set until the condition is no longer true and the sta-
tus bit is cleared by writing a zero.
Linear Feedback Shift Register
Media Access Controller
Media Independent Interface
Not Applicable
In the context of this document, a packet refers to transfers on the USB inter-
face.
Power on Reset
Refers to a reserved bit field or address. Unless otherwise noted, reserved
bits must always be zero for write operations. Unless otherwise noted, values
are not ensured when reading reserved bits. Unless otherwise noted, do not
read or write to reserved addresses.
System Control and Status Register
Serial Management Interface
Transaction Layer Interface
USB Bulk-Out Packet Receiver
USB Bulk-In Packet Transmitter
16 bits
Zero Length USB Packet
 2012-2015 Microchip Technology Inc.
DS00001946A-page 5