LAN9730 Datasheet, PDF (82/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
On detection of one of these events, the PHY begins auto-negotiation by transmitting bursts of Fast Link Pulses (FLP).
These are bursts of link pulses from the 10M transmitter. They are shaped as Normal Link Pulses and can pass uncor-
rupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst consists of up to 33 pulses. The 17 odd-numbered pulses,
which are always present, frame the FLP burst. The 16 even-numbered pulses, which may be present or absent, contain
the data word being transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”.
The data transmitted by an FLP burst is known as a Link Code Word. These are defined fully in IEEE 802.3 clause 28.
In summary, the PHY advertises 802.3 compliance in its selector field (the first 5 bits of the Link Code Word). It adver-
tises its technology ability according to the bits set in register 4 of the SMI registers.
There are 4 possible matches of the technology abilities. In the order of priority these are:
• 100M full-duplex (highest priority)
• 100M half-duplex
• 10M full-duplex
• 10M half-duplex
If the full capabilities of the PHY are advertised (100M, full-duplex), and if the link partner is capable of 10M and 100M,
then auto-negotiation selects 100M as the highest performance mode. If the link partner is capable of half- and full-
duplex modes, then auto-negotiation selects full-duplex as the highest performance operation.
Once a capability match has been determined, the link code words are repeated with the acknowledge bit set. Any dif-
ference in the main content of the link code words at this time will cause auto-negotiation to re-start. Auto-negotiation
will also re-start if not all of the required FLP bursts are received.
Writing register 4 bits [8:5] allows software control of the capabilities advertised by the PHY. Writing register 4 does not
automatically re-start auto-negotiation. Register 0, bit 9 must be set before the new abilities will be advertised. Auto-
negotiation can also be disabled via software by clearing register 0, bit 12.
The device does not support Next Page capability.
4.6.6 PARALLEL DETECTION
If LAN9730/LAN9730i is connected to a device lacking the ability to auto-negotiate (i.e., no FLPs are detected), it is able
to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the
link is presumed to be half-duplex per the IEEE standard. This ability is known as “Parallel Detection. This feature
ensures interoperability with legacy link partners. If a link is formed via parallel detection, then bit 0 in register 6 is cleared
to indicate that the Link Partner is not capable of auto-negotiation. The Ethernet MAC has access to this information via
the management interface. If a fault occurs during parallel detection, bit 4 of register 6 is set.
Register 5 is used to store the Link Partner Ability information, which is coded in the received FLPs. If the Link Partner
is not auto-negotiation capable, then register 5 is updated after completion of parallel detection to reflect the speed capa-
bility of the Link Partner.
4.6.6.1 Re-Starting Auto-Negotiation
Auto-negotiation can be re-started at any time by setting register 0, bit 9. Auto-negotiation will also re-start if the link is
broken at any time. A broken link is caused by signal loss. This may occur because of a cable break, or because of an
interruption in the signal transmitted by the link partner. Auto-negotiation resumes in an attempt to determine the new
link configuration.
If the management entity re-starts auto-negotiation by writing to bit 9 of the control register, the device will respond by
stopping all transmission/receiving operations. Once the break_link_timer is done, in the auto-negotiation state-machine
(approximately 1250 ms) the auto-negotiation will re-start. The link partner will have also dropped the link due to lack of
a received signal, so it too will resume auto-negotiation.
4.6.6.2 Disabling Auto-Negotiation
Auto-negotiation can be disabled by setting register 0, bit 12 to zero. The device will then force its speed of operation
to reflect the information in register 0, bit 13 (speed) and register 0, bit 8 (duplex). The speed and duplex bits in register
0 should be ignored when auto-negotiation is enabled.
DS00001946A-page 82
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