LAN9730 Datasheet, PDF (90/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
4.7.4 EEPROM HOST OPERATIONS
After the EEPROM controller has finished reading (or attempting to read) the EEPROM after a system-level reset, the
host is free to perform other EEPROM operations. EEPROM operations are performed using the EEPROM Command
(E2P_CMD) and EEPROM Data (E2P_DATA) registers. Section 6.3.12, "EEPROM Command Register (E2P_CMD)"
provides an explanation of the supported EEPROM operations.
If the EEPROM operation is the “write location” (WRITE) or “write all” (WRAL) commands, the host must first write the
desired data into the E2P_DATA register. The host must then issue the WRITE or WRAL command using the E2P_CMD
register by setting the EPC_CMD field appropriately. If the operation is a WRITE, the EPC_ADDR field in E2P_CMD
must also be set to the desired location. The command is executed when the host sets the EPC_BSY bit high. The com-
pletion of the operation is indicated when the EPC_BSY bit is cleared.
If the EEPROM operation is the “read location” (READ) operation, the host must issue the READ command using the
E2P_CMD register with the EPC_ADDR set to the desired location. The command is executed when the host sets the
EPC_BSY bit high. The completion of the operation is indicated when the EPC_BSY bit is cleared, at which time the
data from the EEPROM may be read from the E2P_DATA register.
Other EEPROM operations are performed by writing the appropriate command to the E2P_CMD register. The command
is executed when the host sets the EPC_BSY bit high. The completion of the operation is indicated when the EPC_BSY
bit is cleared. In all cases, the host must wait for EPC_BSY to clear before modifying the E2P_CMD register.
Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM,
the host must first issue the EWEN command.
If an operation is attempted, and an EEPROM device does not respond within 30 ms, the device will time-out, and the
EPC time-out bit (EPC_TO) in the E2P_CMD register will be set.
Figure 4-20 illustrates the host accesses required to perform an EEPROM Read or Write operation.
FIGURE 4-20:
EEPROM ACCESS FLOW DIAGRAM
EEPROM Write
EEPROM Read
Idle
Idle
Write Data
Register
Write
Command
Register
Busy Bit = 0
Read
Command
Register
Write
Command
Register
Read
Command
Register
Busy Bit = 0
Read Data
Register
DS00001946A-page 90
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