LAN9730 Datasheet, PDF (126/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
Bits
Description
7 Internal MII Visibility Enable (IME)
This register enables a subset of the MII interface to be visible on unused pins
when configured for the internal Ethernet PHY mode. The pins controlled by
the IME bit are comprised of the pins listed in Table 2-1, "MII Interface Pins"
and the nPHY_INT pin.
0 = The MII signals are not visible. The MII pins function as inputs.
1 = The MII signals are visible. The MII pins function as outputs.
Note: This register has no affect when using an external PHY.
Note:
The IME has priority over the GPIO_CFG register. When IME is
asserted, the pins CRS, MDC, MDIO, COL, TXD3, TXD2, TXD1,
and TXD0 can not be configured for GPIO operation.
6 Discard Errored Received Ethernet Frame (DRP)
This bit will cause errored Ethernet frames to be discarded when enabled.
0 = Do not discard errored Ethernet frames.
1 = Discard errored Ethernet frames.
5 Multiple Ethernet Frames per USB Packet (MEF)
This bit enables the USB transmit direction to pack multiple Ethernet frames
per USB packet whenever possible.
0 = Support no more than one Ethernet frame per USB packet.
1 = Support packing multiple Ethernet frames per USB packet.
Note: The URX supports this mode by default.
4 EEPROM Time-out Control (ETC)
This bit controls the length of time used by the EEPOM controller to detect a
time-out.
0 = Time-out occurs if no response received from EEPROM after 30 ms.
1 = Time-out occurs if no response received from EEPROM after 1.28 µs.
3 Soft Lite Reset (LRST)
Writing 1 generates the lite software reset of the device.
A lite reset will not affect the UDC. Additionally, the contents of the EEPROM
will not be reloaded. This reset will not cause the USB PHY to be discon-
nected. This bit clears after the reset sequence has completed.
2 PHY Select (PSEL)
This bit indicates whether an internal or external Ethernet PHY is being used.
0 = Internal Ethernet PHY is used.
1 = External Ethernet PHY is used.
1 Burst Cap Enable (BCE)
This register enables use of the burst cap register, Section 6.3.14, "Burst Cap
Register (BURST_CAP)".
0 = Burst Cap register is not used to limit the TX burst size.
1 = Burst Cap register is used to limit the TX burst size.
Type
RW
R/W
R/W
R/W
SC
RO
R/W
Default
0b
0b
0b
0b
0b
Note 6-4
0b
DS00001946A-page 126
 2012-2015 Microchip Technology Inc.