LAN9730 Datasheet, PDF (150/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
6.3.21 INTERRUPT ENDPOINT CONTROL REGISTER (INT_EP_CTL)
Address:
068h
Size:
32 bits
This register determines which events cause status to be reported by the interrupt Endpoint. See Section 4.3.1.3, "End-
point 3 (Interrupt)" for more details.
Bits
Description
31 Interrupt Endpoint Always On (INTEP_ON)
When this bit is set, an interrupt packet will always be sent at the interrupt
Endpoint interval.
0 = Only allow the transmission of an interrupt packet when an interrupt
source is enabled and occurs.
30:20
19
1 = Always transmit an interrupt packet at the interrupt interval.
RESERVED
MAC Reset Time Out (MACRTO_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
18 RX FIFO Has Frame Enable (RX_FIFO_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
17 TX Stopped Enable (TXSTOP_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
16 RX Stopped Enable (RXSTOP_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
15 PHY Interrupt Enable (PHY_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
14 Transmitter Error Enable (TXE_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
13 TX Data FIFO Underrun Interrupt Enable (TDFU_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
12 TX Data FIFO Overrun Interrupt Enable (TDFO_EN)
0 = This event can not cause an interrupt packet to be issued.
1 = This event can cause an interrupt packet to be issued.
Type
R/W
Default
0b
RO
-
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
R/W
0b
DS00001946A-page 150
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