LAN9730 Datasheet, PDF (107/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
FIGURE 4-31:
DETAILED GPIOS 0-6 WAKE DETECTION LOGIC
IME
GPIOENn
GPIODIRn
GPIOPOLn
GPIOn
Latch
GPIODn
GPIOn_DET
GPIOn_INT clear
GPIOWKn
Note:
The IME bit is in the Hardware Configuration Register (HW_CFG). General Purpose IO Configuration Reg-
ister (GPIO_CFG) and General Purpose IO Wake Enable and Polarity Register (GPIO_WAKE) must be set
accordingly. Diagram does not represent actual hardware implementation.
FIGURE 4-32:
DETAILED GPIO7 WAKE DETECTION LOGIC
IME
GPIOEN7
GPIODIR7
GPIOPOL7
0
1
GPIOD7
GPIO7_DET
GPIO7
GPIO7_INT clear
GPIOWK7
SUSPEND0
SUSPEND3
PHY_LINK_EN
PHY_LINK_UP
0
1
Latch
 2012-2015 Microchip Technology Inc.
DS00001946A-page 107