LAN9730 Datasheet, PDF (75/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
4.5.8.1 TX Checksum Calculation
The TX checksum calculation is performed using the same operation as the RX checksum shown in Section 4.5.7.1,
with the exception that the calculation starts as indicated by the preamble, and the transmitted checksum is the one’s-
compliment of the final calculation.
Note:
When the TX checksum offload feature is invoked, if the calculated checksum is 0000h, it is left unaltered.
UDP checksums are optional under IPv4, and a zero checksum calculated by the TX checksum offload
feature will erroneously indicate to the receiver that no checksum was calculated, however, the packet will
typically not be rejected by the receiver. Under IPv6, however, according to RFC 2460, the UDP checksum
is not optional. A calculated checksum that yields a result of zero must be changed to FFFFh for insertion
into the UDP header. IPv6 receivers discard UDP packets containing a zero checksum. Thus, this feature
must not be used for UDP checksum calculation under IPv6.
4.5.9 MAC CONTROL AND STATUS REGISTERS (MCSR)
Refer to Section 6.4, "MAC Control and Status Registers" for a complete description of the MCSR.
4.6 10/100 Internal Ethernet PHY
The device integrates an IEEE 802.3 Physical Layer for Twisted Pair Ethernet applications. The PHY can be configured
for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet operation in either full- or half-duplex configura-
tions. The PHY block includes auto-negotiation. Minimal external components are required for the utilization of the inter-
nal PHY.
The device provides an option to use an external PHY in place of the internal PHY. The external PHY can be connected
via the Media Independent Interface (MII) port. This option is useful for supporting Home PNA operations. When an
external PHY is used, the internal PHY must be placed into general power down via a PHY reset (refer to Section 4.6.9,
"PHY Resets" for further information).
Functionally, the internal PHY can be divided into the following sections:
• 100BASE-TX transmit and receive
• 10BASE-T transmit and receive
• Internal MII to the Ethernet Media Access Controller
• Auto-negotiation to automatically determine the best speed and duplex possible
• Management Control to read status registers and write control registers
The device’s Ethernet interface requires a software sequence to be compliant with the IEEE 802.3 Output V_OH+/V_OH-
voltage specification. Microchip has not experienced any functional limitations if this sequence is not implemented,
although IEEE 802.3 compliance may fail by approximately 25 mV if not enabled. The software sequence has been
implemented successfully in the driver released by Microchip. Refer to the Microchip driver source code for an example
of this implementation.
The following pseudo-code structures detail the required sequence:
// Enable access to VOH Compliance registers
REG_ACCESS_ENABLE:
MII_Write: Address 0x14, Data 0x0400
MII_Write: Address 0x14, Data 0x0000
MII_Write: Address 0x14, Data 0x0400
// Enable the VOH Compliance mode
PHY_VOHCOMP_ENABLE:
MII_Write: Address 0x17, Data 0x85E8
(Read MII Address 0x14 until Bit 14 is cleared)
MII_Write: Address 0x14, Data 0x4416
 2012-2015 Microchip Technology Inc.
DS00001946A-page 75