LAN9730 Datasheet, PDF (19/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
TABLE 2-3: JTAG PINS
Num Pins
Name
1
JTAG Test
Port Reset
(Internal PHY
Mode)
Receive Data
0
(External
PHY Mode)
1
JTAG Test
Data Out
(Internal PHY
Mode)
PHY Reset
(External
PHY Mode)
1
JTAG Test
Clock
(Internal PHY
Mode)
Receive Data
1
(External
PHY Mode)
1
JTAG Test
Mode Select
(Internal PHY
Mode)
Receive Data
2
(External
PHY Mode)
1
JTAG Test
Data Input
(Internal PHY
Mode)
Receive Data
3
(External
PHY Mode)
Symbol
nTRST
RXD0
TDO
nPHY_RST
TCK
RXD1
TMS
RXD2
TDI
RXD3
Buffer
Type
IS
(PU)
Description
In Internal PHY Mode, this active-low pin func-
tions as the JTAG test port reset input.
IS
(PD)
In External PHY Mode, this pin functions as the
receive data 0 input from the external PHY.
O8
In Internal PHY Mode, this pin functions as the
JTAG data output.
O8
In External PHY Mode, this active-low pin func-
tions as the PHY reset output.
IS
(PU)
In Internal PHY Mode, this pin functions as the
JTAG test clock. The maximum operating fre-
quency of this clock is 25 MHz.
IS
(PD)
In External PHY Mode, this pin functions as the
receive data 1 input from the external PHY.
IS
(PU)
In Internal PHY Mode, this pin functions as the
JTAG test mode select.
IS
(PD)
In External PHY Mode, this pin functions as the
receive data 2 input from the external PHY.
IS
(PU)
In Internal PHY Mode, this pin functions as the
JTAG data input.
IS
(PD)
In External PHY Mode, this pin functions as the
receive data 3 input from the external PHY.
 2012-2015 Microchip Technology Inc.
DS00001946A-page 19