LAN9730 Datasheet, PDF (8/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
1.2.3 FIFO CONTROLLER (FCT)
The FIFO controller uses a 28 kB internal SRAM to buffer RX and TX traffic. 20 kB are allocated for received Ethernet-
USB traffic (RX buffer), while 8 kB are allocated for USB-Ethernet traffic (TX buffer). Bulk-Out packets from the USB
controller are directly stored into the TX buffer. The FCT is responsible for extracting Ethernet frames from the USB
packet data and passing the frames to the MAC. Ethernet frames are directly stored into the RX buffer and become the
basis for Bulk-In packets. The FCT passes the stored data to the UTX in blocks typically 512 bytes in size.
1.2.4 ETHERNET
LAN9730/LAN9730i integrates an IEEE 802.3 PHY for twisted pair Ethernet applications and a 10/100 Ethernet Media
Access Controller (MAC).
The PHY can be configured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet operation in either
full- or half-duplex configurations. The PHY block includes auto-negotiation, auto-polarity correction, and Auto-MDIX.
Minimal external components are required for the utilization of the integrated PHY.
Optionally, an external PHY may be used via the MII (Media Independent Interface) port, effectively bypassing the inter-
nal PHY. This option allows support for HomePNA and HomePlug applications.
The transmit and receive data paths within the 10/100 Ethernet MAC are independent, allowing for the highest perfor-
mance possible, particularly in full-duplex mode. The Ethernet MAC operates in store and forward mode, utilizing an
independent 2 kB buffer for transmitted frames, and a smaller 128 byte buffer for received frames. The Ethernet MAC
data paths connect to the FIFO controller. The MAC also implements a Control and Status Register (CSR) space used
by the host to obtain status and control its operation.
The Ethernet MAC/PHY supports numerous power management wakeup features, including Magic Packet, Wake on
LAN, and Link Status Change. Eight Wakeup Frame Filters are provided by the device.
1.2.5 POWER MANAGEMENT
The LAN9730/LAN9730i features four variations of USB suspend: SUSPEND0, SUSPEND1, SUSPEND2, and SUS-
PEND3. These modes allow the application to select the ideal balance of remote wakeup functionality and power con-
sumption.
• SUSPEND0: Supports GPIO, Wake On LAN and Magic Packet events. This state reduces power by stopping the
clocks of the MAC and other internal modules.
• SUSPEND1: Supports GPIO and Link Status Change for remote wakeup events. This suspend state consumes
less power than SUSPEND0.
• SUSPEND2: Supports only GPIO assertion for a remote wakeup event. This is the default suspend mode for the
device.
• SUSPEND3: Supports GPIO and Good Packet events. A Good Packet is a received frame passing certain filtering
constraints independent of those imposed on Wake On LAN and Magic Packet frames. This SUSPEND state con-
sumes power at a level similar to the full operational state, however, it allows for power savings in the host CPU.
Refer to Section 4.12, "Wake Events" for more information on the USB suspend states and the wake events supported
in each state.
1.2.6 EEPROM CONTROLLER (EPC)
LAN9730/LAN9730i contains an EEPROM controller for connection to an external EEPROM. This allows for the auto-
matic loading of static configuration data upon Power on Reset, pin reset or software reset. The EEPROM can be con-
figured to load USB descriptors, USB device configuration, and MAC address.
1.2.7 GENERAL PURPOSE I/O
When configured for Internal PHY mode, up to eleven GPIOs are supported. All GPIOs can serve as remote wakeup
events when the LAN9730/LAN9730i is suspended.
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