LAN9730 Datasheet, PDF (94/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the contents of the
E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit is set if the EEPROM does not
respond within 30 ms.
FIGURE 4-27:
EEPROM WRAL CYCLE
tCSL
EECS
EECLK
EEDIO (OUTPUT)
1
0
0
0
1
D7
D0
EEDIO (INPUT)
WRAL CYCLE
Table 4-60, "Required EECLK Cycles", shown below, shows the number of EECLK cycles required for each EEPROM
operation.
TABLE 4-60: REQUIRED EECLK CYCLES
Operation
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
Required EECLK Cycles
10
10
10
10
18
18
18
4.7.4.2 Host Initiated EEPROM Reload
The host can initiate a reload of the EEPROM by issuing the RELOAD command via the E2P Command (E2P_CMD)
register. If the first byte read from the EEPROM is not 0xA5, it is assumed that the EEPROM is not present or not pro-
grammed, and the reload will fail. The Data Loaded bit of the E2P_CMD register indicates a successful reload of the
EEPROM.
Note:
It is not recommended to use the RELOAD command as part of normal operation, as race conditions can
occur with USB Commands that access descriptor data. It is best for the host to issue an SRST to reload
the EEPROM data.
4.7.4.3 EEPROM Command and Data Registers
Refer to Section 6.3.12, "EEPROM Command Register (E2P_CMD)" and Section 6.3.13, "EEPROM Data Register
(E2P_DATA)" for a detailed description of these registers. Supported EEPROM operations are described in these sec-
tions.
4.7.4.4 EEPROM Timing
Refer to Section 7.5.5, "EEPROM Timing" for detailed EEPROM timing specifications.
DS00001946A-page 94
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