LAN9730 Datasheet, PDF (125/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
6.3.5 HARDWARE CONFIGURATION REGISTER (HW_CFG)
Address:
014h
Size:
32 bits
Bits
31:17
16
Description
RESERVED
EEPROM Emulation Enable (EEM)
This bit is used to select the source of descriptor information and configuration
flags when no EEPROM is present.
0 = Use defaults as specified in Section 4.7.2, "EEPROM Defaults" .
1 = Use Descriptor RAM and Attributes Registers.
Type
RO
R/W
Note: This bit affects operation only when an EEPROM is not present.
This bit has no effect when an EEPROM is present.
Note: This field is protected by Reset Protection (RST_PROTECT).
15 Reset Protection (RST_PROTECT)
R/W
Setting this bit protects select fields of certain registers from being affected by
resets other than POR.
Note: This field is protected by Reset Protection (RST_PROTECT).
14:13 RESERVED
RO
12 Bulk-In Empty Response (BIR)
R/W
This bit controls the response to Bulk-In tokens when the RX FIFO is empty.
0 = Respond to the IN token with a ZLP
1 = Respond to the IN token with a NAK
11 Activity LED 80 ms Bypass (LEDB)
R/W
When set, the Activity LED on/off time is reduced to approximately 15 µs/
15 µs.
10:9 RX Data Offset (RXDOFF)
R/W
This field controls the amount of offset, in bytes, that is added to the beginning
of an RX Data packet. The start of the valid data will be shifted by the amount
of bytes specified in this field. An offset of 0-3 bytes is a valid number of offset
bytes.
Note: This register may not be modified after the RX data path has been
enabled.
8 Stall Bulk-Out Pipe Disable (SBP)
R/W
This bit controls the operation of the Bulk-Out pipe when the FCT detects the
loss of sync condition. Refer to Section 4.4.2.5, "TX Error Detection" for
details.
0 = Stall the Bulk-Out pipe when loss of sync detected.
1 = Do not stall the Bulk-Out pipe when loss of sync detected.
Default
-
0b
0b
-
0b
0b
00b
0b
 2012-2015 Microchip Technology Inc.
DS00001946A-page 125