LAN9730 Datasheet, PDF (85/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
4.6.8 PHY POWER-DOWN MODES
There are two power-down modes for the PHY as discussed in the following sections.
4.6.8.1 General Power-Down
This power-down is controlled by register 0, bit 11. In this mode the PHY, except the management interface, is powered-
down and stays in that condition as long as PHY register bit 0.11 is high. When bit 0.11 is cleared, the PHY powers up
and is automatically reset. Refer to Section 6.5.1, "Basic Control Register" for additional information on this register.
Note: For maximum power savings, auto-negotiation should be disabled before enabling the General Power-
Down mode.
4.6.8.2 Energy Detect Power-Down (EDPD)
This power-down mode is activated by setting the EDPWRDOWN bit of the Mode Control/Status Register. In this mode,
when no energy is present on the line, the PHY is powered down (except the one for the management interface, the
SQUELCH circuit, and the ENERGYON logic). The ENERGYON logic is used to detect the presence of valid energy
from 100BASE-TX, 10BASE-T, or auto-negotiation signals.
In this mode, when the ENERGYON bit of the Mode Control/Status Register is low, the PHY is powered-down and noth-
ing is transmitted. When energy is received via link pulses or packets, the ENERGYON bit goes high and the PHY pow-
ers-up. The PHY automatically resets itself into the state prior to power-down and asserts the INT7 bit of the PHY
Interrupt Source Flag Register register. If the ENERGYON interrupt is enabled, this event will cause a PHY interrupt to
the Interrupt Controller and the power management event detection logic. The first and possibly the second packet to
activate ENERGYON may be lost.
When the EDPWRDOWN bit of the Mode Control/Status Register is low, Energy Detect Power-Down is disabled.
When in EDPD mode, the device’s NLP characteristics may be modified. The device can be configured to transmit NLPs
in EDPD via the EDPD TX NLP Enable bit of the EDPD NLP/Crossover TimeRegister. When enabled, the TX NLP time
interval is configurable via the EDPD TX NLP Interval Timer Select field of the EDPD NLP/Crossover TimeRegister.
When in EDPD mode, the device can also be configured to wake on the reception of one or two NLPs. Setting the EDPD
RX Single NLP Wake Enable bit of the EDPD NLP/Crossover TimeRegister will enable the device to wake on reception
of a single NLP. If the EDPD RX Single NLP Wake Enable bit is cleared, the maximum interval for detecting reception
of two NLPs to wake from EDPD is configurable via the EDPD RX NLP Max Interval Detect Select field of the EDPD
NLP/Crossover TimeRegister.
4.6.9 PHY RESETS
In addition to a chip-level reset, the PHY supports two software-initiated resets. These are discussed in the following
sections.
4.6.9.1 PHY Soft Reset via PMT_CTL Register PHY Reset (PHY_RST) Bit
The PHY soft reset is initiated by writing a ‘1’ to the PHY Reset (PHY_RST) bit of the Power Management Control Reg-
ister (PMT_CTL). This self-clearing bit will return to ‘0’ after approximately 2 ms, at which time the PHY reset is com-
plete.
4.6.9.2 PHY Soft Reset via PHY Basic Control Register Bit 15 (PHY Reg. 0.15)
The PHY Reg. 0.15 Soft Reset is initiated by writing a ‘1’ to bit 15 of the PHY’s Basic Control Register. This self-clearing
bit will return to ‘0’ after approximately 256 µs, at which time the PHY reset is complete. The BCR reset initializes the
logic within the PHY, with the exception of register bits marked as NASR (Not Affected by Software Reset).
4.6.10 REQUIRED ETHERNET MAGNETICS
The magnetics selected for use with the device should be an Auto-MDIX style magnetic available from several vendors.
The user is urged to review Microchip Application Note 8.13, Suggested Magnetics for the latest qualified and suggested
magnetics. Vendors and part numbers are provided in this application note.
4.6.11 PHY REGISTERS
Refer to Section 6.5, "PHY Registers" for a complete description of the PHY registers.
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