LAN9730 Datasheet, PDF (17/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
TABLE 2-1: MII INTERFACE PINS (CONTINUED)
Num Pins
Name
1
Transmit Data
0
(Internal PHY
Mode)
Symbol
TXD0
Buffer
Type
IS/O8
(PD)
Transmit Data
0
(External
PHY Mode)
General Pur-
pose I/O 4
(Internal PHY
Mode Only)
EEPROM
Disable Con-
figuration
Strap
TXD0
GPIO4
EEP_DISABLE
O8
(PD)
IS/O8/
OD8
(PU)
IS
(PD)
Description
In Internal PHY Mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 125 for additional information.
In External PHY Mode, this pin functions as the
transmit data 0 output to the external PHY.
This General Purpose I/O pin is fully programma-
ble as either a push-pull output, an open-drain
output or a Schmitt-triggered input.
This strap disables the autoloading of the
EEPROM contents. The assertion of this strap
does not prevent register access to the EEPROM.
0 = EEPROM is recognized if present.
1 = EEPROM is not recognized even if it is pres-
ent.
See Note 2-1 for more information on configura-
tion straps.
 2012-2015 Microchip Technology Inc.
DS00001946A-page 17