LAN9730 Datasheet, PDF (179/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
6.5 PHY Registers
The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC via the MII
Access Register (MII_ACCESS) and MII Access Register (MII_ACCESS). An index is used to access individual PHY
registers. PHY Register Indexes are shown in Table 6-6, "PHY Control and Status Register" below.
Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of the PHY Basic
Control Register (Reset) is set.
TABLE 6-6: PHY CONTROL AND STATUS REGISTER
Index
(In Decimal)
0
1
2
3
4
5
6
16
17
18
26
27
29
30
31
Register Name
Basic Control Register
Basic Status Register
PHY Identifier 1 Register
PHY Identifier 2 Register
Auto Negotiation Advertisement Register
Auto Negotiation Link Partner Ability Register
Auto Negotiation Expansion Register
EDPD NLP/Crossover TimeRegister
Mode Control/Status Register
Special Modes Register
Symbol Error Counter Register
Special Control/Status Indications Register
Interrupt Source Flag Register
Interrupt Mask Register
PHY Special Control/Status Register
 2012-2015 Microchip Technology Inc.
DS00001946A-page 179