LAN9730 Datasheet, PDF (71/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
FIGURE 4-14:
ETHERNET FRAME WITH VLAN TAG AND SNAP HEADER
{DSAP, SSAP, CTRL,
OUI[23:16]}
{OUI[15:0], PID[15:0]}
DST
SRC
8
1
0
0
V
I
D
L
e
n
S
N
A
P
0
S
N
A
P
1
L3 Packet
F
C
S
0123456
1DWORD
Calculate Checksum
FIGURE 4-15:
ETHERNET FRAME WITH MULTIPLE VLAN TAGS AND SNAP HEADER
{DSAP, SSAP, CTRL,
OUI[23:16]}
{OUI[15:0], PID[15:0]}
DST
SRC
8
1
0
0
V
I
D
8
1
0
0
VL
Ie
Dn
S
N
A
P
0
S
N
A
P
1
L3 Packet
F
C
S
01245678
1DWORD
Calculate Checksum
The RXCOE supports a maximum of two VLAN tags. If there are more than two VLAN tags, the VLAN protocol identifier
for the third tag is treated as an Ethernet type field. The checksum calculation will begin immediately after the type field.
The RXCOE resides in the RX path within the MAC. As the RXCOE receives an Ethernet frame, it calculates the 16-bit
checksum. The RXCOE passes the Ethernet frame to the RX FIFO with the checksum appended to the end of the frame.
The RXCOE inserts the checksum immediately after the last byte of the Ethernet frame and before it transmits the status
word. The packet length field in the RX Status Word (refer to Section 4.4.1.2) will indicate that the frame size has
increased by two bytes to accommodate the checksum.
Note: When enabled, the RXCOE calculates a checksum for every received frame.
Setting the RXCOE_EN bit in the Checksum Offload Engine Control Register (COE_CR) enables the RXCOE, while the
RXCOE_MODE bit selects the operating mode. When the RXCOE is disabled, the received data is simply passed
through the RXCOE unmodified.
Note: Software applications must stop the receiver and flush the RX data path before changing the state of the
RXCOE_EN or RXCOE_MODE bits.
Note: When the RXCOE is enabled, automatic pad stripping must be disabled (bit 8 (PADSTR) of the MAC Con-
trol Register (MAC_CR)) and vice versa. These functions cannot be enabled simultaneously.
 2012-2015 Microchip Technology Inc.
DS00001946A-page 71