LAN9730 Datasheet, PDF (153/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
6.3.23 RECEIVE FIFO LEVEL DEBUG REGISTER (DBG_RX_FIFO_LVL)
Address:
070h
Size:
32 bits
Bits
31:30
29:16
Description
RESERVED
RX FIFO Read Level (RXRDLVL)
This is a DWORD count defined as follows:
The count is increased by the number of DWORDs contained in the packet
after the ENTIRE packet has been written into the FIFO.
As a packet is read from the FIFO, it is decremented each time a DWORD is
read.
15:14
13:0
On rewind, it will increase by the number of DWORDS read out of the FIFO.
Note: Rewind case example: On a USB error, whatever was read will be
rewound and the packet will be retransmitted to the host.
RESERVED
RX FIFO Write Level (RXWRLVL)
This is a DWORD count defined as follows:
As a packet is written into the FIFO, it is incremented each time a DWORD is
written.
Whenever a COMPLETE packet has been read from the FIFO, it is decreased
by the number of DWORDs contained in the packet.
On rewind, it is decreased by the number of DWORDs of the packet that has
currently been transferred into the FIFO.
Note: Rewind case example: On an FCS error, whatever was written in
the FIFO will be rewound out.
Type
RO
RO
RO
RO
Default
-
0000h
-
0000h
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DS00001946A-page 153