LAN9730 Datasheet, PDF (134/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
6.3.10 GENERAL PURPOSE IO CONFIGURATION REGISTER (GPIO_CFG)
Address:
028h
Size:
32 bits
This register configures GPIOs 0-7. These GPIOs are not available when using external MII mode. See the PHY_SEL
pin in Table 2-4, "Miscellaneous Pins".
In order for a GPIO to function as a wake event or interrupt source, it must be configured as an input. GPIOs used as
wake events must also be enabled by the GPIO_WAKE register, see Section 6.3.20, "General Purpose IO Wake Enable
and Polarity Register (GPIO_WAKE)".
Bits
31:24
Description
GPIO Enable 0-7 (GPIOENn)
A '1' sets the associated pin to use the default function. When cleared low, the
pin functions as a GPIO signal.
GPIO0 - GPIO7 can be used to mirror internal MII signals when not enabled.
See the IME bit in Section 6.3.5, "Hardware Configuration Register
(HW_CFG)"
23:16
GPIOEN0 - bit 24
GPIOEN1 - bit 25
GPIOEN2 - bit 26
GPIOEN3 - bit 27
GPIOEN4 - bit 28
GPIOEN5 - bit 29
GPIOEN6 - bit 30
GPIOEN7 - bit 31
Note: These GPIOs are disabled after a reset.
GPIO Buffer Type 0-7 (GPIOBUFn)
When set, the output buffer for the corresponding GPIO signal is configured
as a push/pull driver. When cleared, the corresponding GPIO signal is config-
ured as an open-drain driver.
GPIOBUF0 - bit 16
GPIOBUF1 - bit 17
GPIOBUF2 - bit 18
GPIOBUF3 - bit 19
GPIOBUF4 - bit 20
GPIOBUF5 - bit 21
GPIOBUF6 - bit 22
GPIOBUF7 - bit 23
15:8 GPIO Direction 0-7 (GPIODIRn)
When set, enables the corresponding GPIO as output. When cleared, the
GPIO is enabled as an input.
GPIODIR0 - bit 8
GPIODIR1 - bit 9
GPIODIR2 - bit 10
GPIODIR3 - bit 11
GPIODIR4 - bit 12
GPIODIR5 - bit 13
GPIODIR6 - bit 14
GPIODIR7 - bit 15
Type
R/W
R/W
R/W
Default
FFh
00h
00h
DS00001946A-page 134
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