LAN9730 Datasheet, PDF (109/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
Wakeup frame detection must be enabled in the MAC before detection can occur. Likewise, the energy detect interrupt
must be enabled in the PHY before this interrupt can be used as a wake event. If the device is properly configured, the
internal wake event interrupt will cause the assertion of the remote_wake signal on detection of a wake event.
4.12.1.2.2 Good Frame Detection
To wakeup on reception of a frame passing the filtering constraints set solely by the MAC Control Register (MAC_CR),
the enables for all Wake On LAN events contained in the Wakeup Control and Status Register (WUCSR) must be
cleared and the desired constraints must be selected in MAC_CR. The setting of the Wake On LAN Enable (WOL_EN)
bit of the Power Management Control Register (PMT_CTL) is a “don’t care”. The logic will generate an internal wake
event interrupt when the MAC detects a frame passing the filtering constraints (Good Frame). The Wake On LAN bit of
the Wakeup Status (WUPS) field of the Power Management Control Register (PMT_CTL) is used to signal wakeup due
to reception of the Good Frame.
Note: Good Frame reception resulting in the generation of a remote_wake event may only occur when in the
SUSPEND3 state.
4.12.1.2.3 GPIO Pin
GPIO pins 0 through 10 may cause the generation of a remote_wake event when properly configured and in any of the
SUSPEND states. GPIO pins 0 through 7 each have a control bit (GPIOENx, 0<=x<=7) in the General Purpose IO Con-
figuration Register (GPIO_CFG) that is used to enable the GPIO pin to generate a remote_wake event. GPIO pins 8
through 10 have no specific enable bit. The corresponding enable signal for these pins (GPIOENy, 8<=y<=10) is derived
from the manner in which the pin is programmed. Ten GPIO wakeup status bits (GPIOWKy, 8<=y<=10) are available to
determine the source of the event.
4.12.1.2.4 PHY Link Up
GPIO7 may be programmed to signal a wakeup in the SUSPEND0 or SUSPEND3 state on occurrence of a PHY Link
Up. The PHY Link Up Enable (PHY_LINKUP_EN) bit of the General Purpose IO Wake Enable and Polarity Register
(GPIO_WAKE) must be set to use GPIO7 for this purpose. When used in this mode, the signal connected to the device’s
pin is ignored.
4.12.2 ENABLING WAKE EVENTS
4.12.2.1 Enabling GPIO Wake Events
The host system must perform the following steps to enable the device to assert a remote_wake event on detection of
a GPIO wake event.
1. The GPIO pin is programmed to facilitate generation of the wake event. If the pin is one of GPIO0 through GPIO7,
the pin must be enabled to generate the event (GPIOENx must be clear in the General Purpose IO Configuration
Register (GPIO_CFG)). If the pin is one of GPIO8 through GPIO10, the pin must be programmed as an input
GPIO pin (the GPCTL and GPDIR fields for the pin in the LED General Purpose IO Configuration Register
(LED_GPIO_CFG) must be set to 00b and 0, respectively). In addition, the pin must be enabled for wakeup and
its desired polarity specified in the GPIO Wake 0-10 (GPIOWKn) and GPIO Polarity 0-10 (GPIOPOLn) fields,
respectively, of the General Purpose IO Wake Enable and Polarity Register (GPIO_WAKE).
2. The host places the device in the any one of the SUSPEND states by setting the Suspend Mode (SUSPEND_-
MODE) field of the Power Management Control Register (PMT_CTL) to indicate the desired SUSPEND state,
then sends suspend signaling.
On detection of an enabled GPIO wake event, the device will transition back to the NORMAL state and signal a
remote_wake event. The host may then examine the GPIO [10:0] (GPIOx_INT) status bits of the Interrupt Status Reg-
ister (INT_STS) to determine the source of the wakeup.
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DS00001946A-page 109