LAN9730 Datasheet, PDF(112/222 Page) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

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LAN9730 Datasheet, PDF (112/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

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LAN9730/LAN9730i

4.13 Resets

The device has the following chip level reset sources:

â¢ Power on Reset (POR)

â¢ External Chip Reset (nRESET)

â¢ Lite Reset (LRST)

â¢ Soft Reset (SRST)

â¢ USB Reset

â¢ PHY Software Reset

â¢ nTRST

4.13.1 POWER ON RESET (POR)

A Power on Reset occurs whenever power is initially applied to the device, or if power is removed and reapplied to the

device. A timer within the device will assert the internal reset for approximately 22 ms.

Note: The EEPROM contents are loaded by this reset.

Note: After the assertion of the POR, the internal Ethernet PHY is put into general power down mode.

4.13.2 EXTERNAL CHIP RESET (NRESET)

A hardware reset will occur when the nRESET pin is driven low. The READY bit in the PMT_CTRL register can be read

by the host, and will read back a â0â until the hardware reset is complete. Upon completion of the hardware reset, the

READY bit in PMT_CTRL is set high.

After the READY bit is set, the device can be configured via its control registers. The nRESET pin is pulled-high inter-

nally by the device and can be left unconnected if unused. If used, nRESET must be driven low for a minimum period

as defined in Section 7.5.4, "Reset and Configuration Strap Timing". If nRESET is unused, the device must be reset

following power-up via a soft reset (SRST).

Note: After the assertion of nRESET, the internal Ethernet PHY is put into General Power-Down mode.

4.13.3 LITE RESET (LRST)

This reset is initiated via the LRST bit in the Section 6.3.5, "Hardware Configuration Register (HW_CFG)". It will reset

the entire chip with the exception of the USB Device Controller and the USB PHY (UDC, parts of the CTL, and the HSIC

interface). The PLL is not turned off.

Note: This reset does not cause the USB contents from the EEPROM to be reloaded.

Note: This reset does not place the device into the Unconfigured state.

Note:

After the LRST, the USB pipes corresponding to the Bulk-In, Bulk-Out, and Interrupt Endpoints must be

reset. This process entails clearing the deviceâs ENDPOINT_HALT feature and resetting the data toggle on

the host side.

DS00001946A-page 112

ï£ 2012-2015 Microchip Technology Inc.

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