LAN9730 Datasheet, PDF (168/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
6.4.3 MAC ADDRESS LOW REGISTER (ADDRL)
Address:
108h
Size:
32 bits
This register contains the lower 32 bits of the physical address of the MAC, where ADDRL[7:0] is the first octet of the
Ethernet frame.
Note: This register is protected by Reset Protection (RST_PROTECT).
Bits
Description
31:0 Physical Address [31:0]
This field contains the lower 32 bits (31:0) of the Physical Address of this MAC
device.
Type
R/W
Default
FFFF_FFFFh
Table 6-5 illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the reception of the Ethernet
physical address.
TABLE 6-5: ADDRL, ADDRH BYTE ORDERING
ADDRL, ADDRH
Order of Reception on Ethernet
ADDRL[7:0]
1^st
ADDRL[15:8]
2^nd
ADDRL[23:16]
3^rd
ADDRL[31:24]
4^th
ADDRH[7:0]
5^th
ADDRH[15:8]
6^th
As an example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the ADDRL and ADDRH registers would
be programmed as shown in Figure 6-1.
FIGURE 6-1:
EXAMPLE ADDRL, ADDRH ADDRESS ORDERING
31 24 23 16 15 8 7 0
xx
xx
0xBC 0x9A
ADDRH
31 24 23 16 15 8 7
0
0x78 0x56 0x34 0x12
ADDRL
DS00001946A-page 168
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