LAN9730 Datasheet, PDF (34/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
4.3.1.3 Endpoint 3 (Interrupt)
The Interrupt Endpoint is responsible for indicating device status at each polling interval. The Interrupt Endpoint is imple-
mented via the CTL module. When the Endpoint is accessed, the Interrupt packet specified in Table 4-2 is presented to
the host.
TABLE 4-2: INTERRUPT PACKET FORMAT
Bits
31:20
19
18
17
16
15
14
13
12
11
10:0
Description
RESERVED
MACRTO_INT
RX FIFO Has Frame. The RX FIFO has at least one complete Ethernet frame.
TXSTOP_INT
RXSTOP_INT
PHY_INT
TXE
TDFU
TDFO
RXDF_INT
GPIO_INT
If there is no interrupt status to report, the device responds with a NACK.
Note: The polling interval is static and set through the EEPROM. The host can change the polling interval by
updating the contents of the EEPROM and resetting the part.
The interrupt status can be cleared by writing to Interrupt Status Register (INT_STS).
4.3.1.4 Endpoint 0 (Control)
The Control Endpoint is handled by the CTL (USB Control) module. The CTL module is responsible for handling USB
standard commands, as well as USB vendor commands. In order to support these commands, the CTL must compile
a variety of statistics and store the programmable portions of the USB descriptors. The supported USB commands can
be found in Section 4.3.2, "USB Standard Commands".
DS00001946A-page 34
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