LAN9730 Datasheet, PDF (144/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
6.3.15 DATA PORT SELECT REGISTER (DP_SEL)
Address:
040h
Size:
32 bits
Before accessing the internal RAMs, the TESTEN bit must be set. It is not valid to use the RAM data port during run time.
The RAM Test Mode Select chooses which internal RAM to access.
The Data Port Ready bit indicates when the data port RAM access has been completed. In the case of a read operation,
this indicates when the read data has been stored in the DP_DATA register.
Bits
Description
31 Data Port Ready (DPRDY)
0 = Data port is processing a transaction.
1 = Data port is ready.
30:3 RESERVED
2:1 RAM Test Select (RSEL)
Selects which RAM to access.
00 = FCT Data RAM
01 = EEPROM storage RAM
10 = TX TLI RAM
11 = RX TLI RAM
0 RAM Test Mode Enable (TESTEN)
Put all test accessible RAMs in test mode.
Type
RO
Default
1b
RO
-
R/W
0b
R/W
0b
DS00001946A-page 144
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