LAN9730 Datasheet, PDF (210/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
7.6 Clock Circuit
The device can accept either a 25 MHz crystal (preferred) or a 25 MHz single-ended clock oscillator (+/-50ppm) input.
If the single-ended clock oscillator method is implemented, XO should be left unconnected and XI should be driven with
a nominal 0-3.3 V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals
(XI/XO). Either a 300 µW or 100 µW 25 MHz crystal may be utilized. The 300 µW 25 MHz crystal specifications are
detailed in Section 7.6.1. The 100 µW 25 MHz crystal specifications are detailed in Section 7.6.2.
7.6.1 300 µW 25 MHZ CRYSTAL SPECIFICATIONS
When utilizing a 300 µW 25 MHz crystal, the following circuit design (Figure 7-11) and specifications (Table 7-23) are
required to ensure proper operation.
FIGURE 7-11:
300 µW 25 MHZ CRYSTAL CIRCUIT
LAN9730
XO
XI
Y1
C₁
C₂
TABLE 7-23: 300 µW CRYSTAL SPECIFICATIONS
Parameter
Crystal Cut
Crystal Oscillation Mode
Crystal Calibration Mode
Frequency
Frequency Tolerance @ 25^oC
Frequency Stability Over Temp
Frequency Deviation Over Time
Total Allowable PPM Budget
Shunt Capacitance
Load Capacitance
Drive Level
Equivalent Series Resistance
Operating Temperature Range
XI Pin Capacitance
XO Pin Capacitance
Symbol
Min.
AT, typ
Fundamental Mode
Parallel Resonant Mode
F_fund
-
F_tol
-
F_temp
-
F_age
-
-
C_O
-
C_L
-
P_W
300
R₁
-
Note 7-18
-
-
Nom.
25.000
-
-
+/-3 to 5
-
7 typ
20 typ
-
-
-
3 typ
3 typ
Max.
Unit
Note
-
+/-50
+/-50
-
+/-50
-
-
-
50
Note 7-19
-
-
MHz
PPM
PPM
PPM
PPM
pF
pF
µW
Ohm
o_C
pF
pF
Note 7-15
Note 7-15
Note 7-16
Note 7-17
Note 7-20
Note 7-20
DS00001946A-page 210
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