LAN9730 Datasheet, PDF (189/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
6.5.10 SPECIAL MODES REGISTER
Index (In Decimal): 18
Size:
16 bits
Bits
Description
15:8 RESERVED
7:5 MODE
PHY Mode of operation. Refer to Table 6-7 for more details.
4:0 PHYADD
PHY Address. The PHY Address is used for the SMI address.
Type
RO
R/W
NASR
R/W
NASR
Default
-
111b
00001b
TABLE 6-7: MODE CONTROL
MODE
Mode Definitions
000b
001b
010b
011b
100b
101b
110b
111b
10BASE-T half duplex. Auto-negotiation disabled.
10BASE-T full duplex. Auto-negotiation disabled.
100BASE-TX half duplex. Auto-negotiation disabled.
CRS is active during Transmit & Receive.
100BASE-TX full duplex. Auto-negotiation disabled.
CRS is active during Receive.
100BASE-TX half duplex is advertised. Auto-negoti-
ation enabled. CRS is active during Transmit &
Receive.
Repeater mode. Auto-negotiation enabled.
100BASE-TX half duplex is advertised. CRS is
active during Receive.
RESERVED - Do not set the device in this mode.
All capable. Auto-negotiation enabled.
Default Register Bit Values
Register 0
Register 4
[13,12,8]
[8,7,6,5]
000
N/A
001
N/A
100
N/A
101
N/A
110
0100
110
0100
N/A
N/A
X1X
1111
 2012-2015 Microchip Technology Inc.
DS00001946A-page 189