LAN9730 Datasheet, PDF (12/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
TABLE 2-1: MII INTERFACE PINS
Num Pins
Name
1
Receive Error
(Internal PHY
Mode)
Symbol
RXER
Receive Error
(External
PHY Mode)
RXER
1
Transmit
Error
(Internal PHY
Mode)
TXER
Transmit
Error
(External
PHY Mode)
1
Transmit
Enable
(Internal PHY
Mode)
TXER
TXEN
Transmit
Enable
(External
PHY Mode)
TXEN
1
Receive Data
RXDV
Valid
(Internal PHY
Mode)
Receive Data
Valid
(External
PHY Mode)
RXDV
1
Receive
RXCLK
Clock
(Internal PHY
Mode)
Receive
Clock
(External
PHY Mode)
RXCLK
Buffer
Type
IS/O8
(PD)
IS
(PD)
IS/O8
(PD)
O8
(PD)
Description
In Internal PHY Mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 125 for additional information.
In External PHY Mode, the signal on this pin is
input from the external PHY and indicates a
receive error in the packet.
In Internal PHY Mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 125 for additional information.
In External PHY Mode, this pin functions as an
output to the external PHY and indicates a trans-
mit error.
IS/O8
(PD)
O8
(PD)
In Internal PHY Mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 125 for additional information.
In External PHY Mode, this pin functions as an
output to the external PHY and indicates valid
data on TXD[3:0].
IS/O8
(PD)
IS
(PD)
In Internal PHY Mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 125 for additional information.
In External PHY Mode, the signal on this pin is
input from the external PHY and indicates valid
data on RXD[3:0].
IS/O8
(PD)
IS
(PD)
In Internal PHY Mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 125 for additional information.
In External PHY Mode, this pin is the receiver
clock input from the external PHY.
DS00001946A-page 12
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