LAN9730 Datasheet, PDF (14/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
TABLE 2-1: MII INTERFACE PINS (CONTINUED)
Num Pins
Name
1
Management
Data
(Internal PHY
Mode)
Symbol
MDIO
Buffer
Type
IS/O8
(PU)
Management
Data
(External
PHY Mode)
General Pur-
pose I/O 1
(Internal PHY
Mode Only)
MDIO
GPIO1
IS/O8
(PD)
IS/O8/
OD8
(PU)
1
Management
Clock
(Internal PHY
Mode)
MDC
Management
Clock
(External
PHY Mode)
General Pur-
pose I/O 2
(Internal PHY
Mode Only)
MDC
GPIO2
IS/O8
(PU)
O8
(PD)
IS/O8/
OD8
(PU)
Description
In Internal PHY Mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 125 for additional information.
In External PHY Mode, this pin provides the man-
agement data to/from the external PHY.
This General Purpose I/O pin is fully programma-
ble as either a push-pull output, an open-drain
output or a Schmitt-triggered input.
Note:
This pin may serve as the
PME_MODE_SEL input when Internal
PHY and PME Modes of operation are
in effect. Refer to Chapter 5.0, "PME
Operation" for additional information.
In Internal PHY Mode, this pin can be configured
to display the respective internal MII signal. Refer
to the Internal MII Visibility Enable (IME) bit of the
Hardware Configuration Register (HW_CFG) on
page 125 for additional information.
In External PHY Mode, this pin outputs the man-
agement clock to the external PHY.
This General Purpose I/O pin is fully programma-
ble as either a push-pull output, an open-drain
output or a Schmitt-triggered input.
DS00001946A-page 14
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