LAN9730 Datasheet, PDF (51/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
TABLE 4-40: RX STATUS WORD FORMAT (CONTINUED)
Bits
Description
6
Collision Seen
When set, this bit indicates that the frame has seen a collision after the collision window. This indicates
that a late collision has occurred.
5
Frame Type
When set, this bit indicates that the frame is an Ethernet-type frame (length/type field in the frame is
greater than 1500). When reset, it indicates the incoming frame was an 802.3 type frame. This bit is not
set for Runt frames less than 14 bytes.
4
Receive Watchdog Time-Out
When set, this bit indicates that the incoming frame is greater than 2048 bytes through 2560 bytes,
therefore expiring the Receive Watchdog Timer.
3
MII Error
When set, this bit indicates that a receive error (RX_ER asserted) was detected during frame reception.
2
Dribbling Bit
When set, this bit indicates that the frame contained a no-integer multiple of 8 bits. This error is
reported only if the number of dribbling bits in the last byte is 4 in the MII operating mode, or at least 3
in the 10 Mbps operating mode. This bit will not be set when the Collision Seen bit[6] is set. If set and
the CRC error[1] bit is reset, then the frame is considered to be valid.
1
CRC Error
When set, this bit indicates that a CRC error was detected. This bit is also set when the RX_ER pin is
asserted during the reception of a frame even though the CRC may be correct. This bit is not valid if the
received frame is a Runt frame, or a late collision was detected or when the Watchdog time-out occurs.
0
RESERVED
4.4.1.3 Flushing the RX FIFO
The device allows for the host to flush the entire contents of the FCT RX FIFO. When a flush is activated, the read and
write pointers of the RX FIFO are returned to their reset state.
Before flushing the RX FIFO, the device’s receiver must be stopped, as specified in Section 4.4.1.4. Once the receiver
stop completion is confirmed, the Receive FIFO Flush bit can be set in the Receive Configuration Register (RX_CFG)
on page 123 to initiate the flush operation. This bit is cleared after the flush is complete.
4.4.1.4 Stopping and Starting the Receiver
To stop the receiver, the host must clear the Receiver Enable (RXEN) bit in the MAC Control Register (MAC_CR) on
page 163. When the receiver is halted, the RXSTOP_INT will be pulsed. Once stopped, the host can optionally clear
the RX Status and RX FIFOs. The host must re-enable the receiver by setting the RXEN bit.
4.4.2 TX PATH (USB -> ETHERNET)
The 8 kB TX FIFO buffers USB Bulk-Out packets received by the URX. The FCT is responsible for extracting the Ether-
net frames embedded in the USB Bulk-Out packets and passing them to the TLI. The Ethernet frames are segmented
across the USB packets by the host drivers.
The FCT manages the writing of data into the TX FIFO through the use of two pointers - the tx_wr_ptr and the tx_wr_h-
d_ptr. These pointers are used to manage the storing of USB Bulk-Out packets. They support rewinding the stored USB
packet, in the event that the Bulk-Out packet is errored and needs to be retransmitted by the host. The write side of the
FCT does not perform any processing on the USB packet data. The read side of the TX FIFO is responsible for extract-
ing the Ethernet frames. The Ethernet frames may be split across multiple buffers, as shown in Figure 4-5.
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DS00001946A-page 51