LAN9730 Datasheet, PDF (88/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
Table 4-58 describes the GPIO PME flags.
TABLE 4-58: GPIO PME FLAGS
Bits
Description
7 GPIO PME Enable
Setting this bit enables the assertion of the GPIO0 or GPIO8 pin, as a result of a Wakeup (GPIO) pin,
Magic Packet, or PHY Link Up. The host processor may use the GPIO0/GPIO8 pin to asynchronously
wake up, in a manner analogous to a PCI PME pin. GPIO0 signals the event when operating in Internal
PHY mode, while GPIO8 signals the event when operating in External PHY mode. Internal or External
PHY mode of operation is dictated by the PHY_SEL pin.
0 = The device does not support GPIO PME signaling.
1 = The device supports GPIO PME signaling.
Note: When this bit is 0, the remaining GPIO PME parameters in this flag byte are ignored.
6 GPIO PME Configuration
This bit selects whether the GPIO PME is signaled on the GPIO pin as a level or a pulse. If pulse is
selected, the duration of the pulse is determined by the setting of the GPIO PME Length bit of this flag
byte. The level of the signal or the polarity of the pulse is determined by the GPIO PME Polarity bit of this
flag byte.
0 = GPIO PME is signaled via a level.
1 = GPIO PME is signaled via a pulse.
Note: If GPIO PME Enable is 0, this bit is ignored.
5 GPIO PME Length
When the GPIO PME Configuration bit of this flag byte indicates that the GPIO PME is signaled by a pulse
on the GPIO pin, this bit determines the duration of the pulse.
0 = GPIO PME pulse length is 1.5 ms.
1 = GPIO PME pulse length is 150 ms.
Note: If GPIO PME Enable is 0, this bit is ignored.
4 GPIO PME Polarity
Specifies the level of the signal or the polarity of the pulse used for GPIO PME signaling.
0 = GPIO PME signaling polarity is low.
1 = GPIO PME signaling polarity is high.
Note: If GPIO PME Enable is 0, this bit is ignored.
3 GPIO PME Buffer Type
This bit selects the output buffer type for GPIO0/GPIO8.
0 = Open drain driver/open source
1 = Push-pull driver
Note: Buffer type = 0, polarity = 0 implies open drain
Buffer type = 0, polarity = 1 implies open source
Note: If GPIO PME Enable is 0, this bit is ignored.
2 GPIO PME WOL Select
Three types of wakeup events are supported: Magic Packet, PHY Link Up, and Wakeup Pin(s) assertion.
Wakeup Pin(s) are selected via the GPIO Wake 0-10 (GPIOWKn) field of the General Purpose IO Wake
Enable and Polarity Register (GPIO_WAKE). The Wakeup Enables are specified in bytes 1Eh and 1Fh of
the EEPROM. This bit selects whether Magic Packet or Link Up wakeup events are supported.
0 = Magic Packet wakeup supported.
1 = PHY Link Up wakeup supported (not supported in External PHY mode).
Note: If GPIO PME Enable is 0, this bit is ignored.
DS00001946A-page 88
 2012-2015 Microchip Technology Inc.