LAN9730 Datasheet, PDF (59/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
4.4.2.8 TX Example 2
In this example, a single 183-byte Ethernet frame will be transmitted. This packet is in a single buffer as follows:
• 2 bytes Data Start Offset
• 183 bytes of payload data
Figure 4-7 illustrates the TX Command structure for this example, and also shows how data is passed to the TX data
FIFO. Note that the packet resides in a single TX Buffer, therefore both the FS and LS bits are set in TX Command A.
FIGURE 4-7:
TX EXAMPLE 2
.
.
.
USB Packet 0
TX Command B
TX Command A
183 Byte Payload
TX Command B
TX Command A
TX Command A
Data Start Offset = 2
First Segment = 1
Last Segment = 1
Buffer Size = 183
TX Command B
Frame Length = 183
183 Byte
Ethernet
Frame
4.4.2.9 TX Example 3
In this example a single, 111-byte Ethernet frame will be transmitted with a TX checksum. This packet is divided into
four buffers. The four buffers are as follows:
Buffer 0:
• 0 byte Data Start Offset
• 4 bytes Checksum Preamble
Buffer 1:
• 3 bytes Data Start Offset
• 79 bytes of payload data
Buffer 2:
• 0 byte Data Start Offset
• 15 bytes of payload data
Buffer 3:
• 2 bytes Data Start Offset
• 17 bytes of payload data
Figure 4-8 illustrates the TX Command structure for this example, and also shows how data is passed to the TX data
FIFO.
Note:
When enabled, the TX Checksum Preamble is pre-pended to the data to be transmitted. The FS bit in TX
Command A, the TX Checksum Enable bit (CK) of TX Command B, and the TXCOE_EN bit of the
COE_CR register must all be set for the TX checksum to be generated. FS must not be set for subsequent
fragments of the same packet. Refer to Section 4.5.8, "Transmit Checksum Offload Engine (TXCOE)" for
further information.
 2012-2015 Microchip Technology Inc.
DS00001946A-page 59