LAN9730 Datasheet, PDF (69/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
4.5.6 MAGIC PACKET DETECTION
Setting the Magic Packet Enable (MPEN) bit in the Wakeup Control and Status Register (WUCSR), places the MAC in
the Magic Packet Detection mode. In this mode, normal data reception is disabled, and detection logic within the MAC
examines receive data for a Magic Packet. When a Magic Packet is received, the Magic Packet Received (MPR) bit in
the WUCSR is set, the device places itself in a fully operational state, and remote wakeup is issued. The host will then
resume the device and read the WUSCR register to determine the condition that caused the remote wakeup. Upon
determining that the MPR bit is set, the host will know reception of a Magic Packet was the cause. The host will then
clear the MPR bit, and clear the MPEN bit to resume normal receive operation. Refer to Section 6.4.12, "Wakeup Control
and Status Register (WUCSR)" for additional information on this register.
In Magic Packet mode, the Power Management Logic constantly monitors each frame addressed to the node for a spe-
cific Magic Packet pattern. It checks only packets with the MAC’s address or a broadcast address to meet the Magic
Packet requirement. The Power Management Logic checks each received frame for the pattern 48h
FF_FF_FF_FF_FF_FF after the destination and source address field.
Then the function looks in the frame for 16 repetitions of the MAC address without any breaks or interruptions. In case
of a break in the 16 address repetitions, the PMT function scans for the 48'h FF_FF_FF_FF_FF_FF pattern again in the
incoming frame.
The 16 repetitions may be anywhere in the frame but must be preceded by the synchronization stream. The device will
also accept a multicast frame, as long as it detects the 16 duplications of the MAC address. If the MAC address of a
node is 00h 11h 22h 33h 44h 55h, then the MAC scans for the following data sequence in an Ethernet Frame:
Destination Address Source Address ……………FF FF FF FF FF FF
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
…CRC
4.5.7 RECEIVE CHECKSUM OFFLOAD ENGINE (RXCOE)
The receive checksum offload engine provides assistance to the host by calculating a 16-bit checksum for a received
Ethernet frame. The RXCOE readily supports the following IEEE 802.3 frame formats:
• Type II Ethernet frames
• SNAP encapsulated frames
• Support for up to 2, 802.1q VLAN tags
The resulting checksum value can also be modified by software to support other frame formats.
The RXCOE has two modes of operation. In mode 0, the RXCOE calculates the checksum between the first 14 bytes
of the Ethernet frame and the FCS. This is illustrated in Figure 4-10.
FIGURE 4-10:
RXCOE CHECKSUM CALCULATION
T
DST
SRC
Y
P
E
Frame Data
F
C
S
Calculate Checksum
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