LAN9730 Datasheet, PDF (204/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
7.5.5 EEPROM TIMING
The following specifies the EEPROM timing requirements for the device:
FIGURE 7-5:
EEPROM TIMING
EECS
EECLK
EEDO
EEDI
EEDI (VERIFY)
t_cshckh
t_ckcyc
t_ckh t_ckl
t_dvckh ^tckhinvld
t_dsckh
t_cshdv
t_dhckh
t_csl
t_cklcsl
t_dhcsl
TABLE 7-17: EEPROM TIMING VALUES
Symbol
t_ckcyc
t_ckh
t_ckl
t_cshckh
t_cklcsl
t_dvckh
t_ckhinvld
t_dsckh
t_dhckh
t_cshdv
t_dhcsl
t_csl
Description
EECLK cycle time
EECLK high time
EECLK low time
EECS high before rising edge of EECLK
EECLK falling edge to EECS low
EEDO valid before rising edge of EECLK
EEDO invalid after rising edge EECLK
EEDI setup to rising edge of EECLK
EEDI hold after rising edge of EECLK
EEDIO valid after EECS high (VERIFY)
EEDIO hold after EECS low (VERIFY)
EECS low
Min
TYP
Max
Unit
1110
550
1130
ns
570
ns
550
570
ns
1070
ns
30
ns
550
ns
550
ns
90
ns
0
ns
600
ns
0
ns
1070
ns
DS00001946A-page 204
 2012-2015 Microchip Technology Inc.