LAN9730 Datasheet, PDF (178/222 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

LAN9730/LAN9730i
6.4.13 CHECKSUM OFFLOAD ENGINE CONTROL REGISTER (COE_CR)
Address:
130h
Size:
32 bits
This register controls the RX and TX checksum offload engines.
Bits
31:17
16
Description
RESERVED
TX Checksum Offload Engine Enable (TX_COE_EN)
TX_COE_EN may only be changed if the TX path is disabled. If it is desired to
change this value during run time, it is safe to do so only after the MAC is dis-
abled and the TLI is empty.
0 = The TXCOE is bypassed.
1 = The TXCOE is enabled.
15:2 RESERVED
1 RX Checksum Offload Engine Mode (RX_COE_MODE)
This register indicates whether the COE will check for VLAN tags or a SNAP
header prior to beginning its checksum calculation. In its default mode, the
calculation will always begin 14 bytes into the frame.
RX_COE_MODE may only be changed if the RX path is disabled. If it is
desired to change this value during run time, it is safe to do so only after the
MAC is disabled and the TLI is empty.
0 = Begin checksum calculation after first 14 bytes of Ethernet Frame.
1 = Begin checksum calculation at start of L3 packet by adjusting for VLAN
tags and/or SNAP header.
0 RX Checksum Offload Engine Enable (RX_COE_EN)
RX_COE_EN may only be changed if the RX path is disabled. If it is desired
to change this value during run time, it is safe to do so only after the MAC is
disabled and the TLI is empty.
0 = The RXCOE is bypassed.
1 = The RXCOE is enabled.
Type
RO
R/W
RO
R/W
R/W
Default
-
0b
-
0b
0b
DS00001946A-page 178
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