SAM7X128_14 Datasheet, PDF (99/662 Pages) ATMEL Corporation – ARM-based Flash MCU

19. Embedded Flash Controller (EFC)
19.1 Overview
The Embedded Flash Controller (EFC ) is a part of the Memory Controller and ensures the interface of the Flash block
with the 32-bit internal bus. It increases performance in Thumb Mode for Code Fetch with its system of 32-bit buffers. It
also manages the programming, erasing, locking and unlocking sequences using a full set of commands.
The AT91SAM7X512 is equipped with two EFCs, EFC0 and EFC1. EFC1 does not feature the Security bit and GPNVM
bits. The Security and GPNVM bits embedded only on EFC0 apply to the two blocks in the AT91SAM7X512.
19.2 Functional Description
19.2.1 Embedded Flash Organization
The Embedded Flash interfaces directly to the 32-bit internal bus. It is composed of several interfaces:
 One memory plane organized in several pages of the same size
 Two 32-bit read buffers used for code read optimization (see “Read Operations” on page 100).
 One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is
write-only and accessible all along the 1 MByte address space, so that each word can be written to its final
address (see “Write Operations” on page 102).
 Several lock bits used to protect write and erase operations on lock regions. A lock region is composed of several
consecutive pages, and each lock region has its associated lock bit.
 Several general-purpose NVM bits. Each bit controls a specific feature in the device. Refer to the product definition
section to get the GPNVM assignment.
The Embedded Flash size, the page size and the lock region organization are described in the product definition section.
Table 19-1. Product Specific Lock and General-purpose NVM Bits
SAM7X512
SAM7X256
SAM7X128 Denomination
3
3
3
Number of General-purpose NVM bits
32
16
8
Number of Lock Bits
SAM7X Series [DATASHEET] 99
6120K–ATARM–11-Feb-14