SAM7X128_14 Datasheet, PDF (271/662 Pages) ATMEL Corporation – ARM-based Flash MCU

29.5 Functional Description
29.5.1 Transfer format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an
acknowledgement. The number of bytes per transfer is unlimited (see Figure 29-4 on page 271).
Each transfer begins with a START condition and terminates with a STOP condition (see Figure 29-3 on page 271).
 A high-to-low transition on the TWD line while TWCK is high defines the START condition.
 A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 29-3. START and STOP Conditions
TWD
TWCK
Start
Stop
Figure 29-4. Transfer Format
TWD
TWCK
Start Address R/W Ack
Data
Ack
Data
Ack Stop
29.5.2 Modes of Operation
The TWI has two modes of operation:
 Master transmitter mode
 Master receiver mode
The TWI Control Register (TWI_CR) allows configuration of the interface in Master Mode. In this mode, it generates the
clock according to the value programmed in the Clock Waveform Generator Register (TWI_CWGR). This register defines
the TWCK signal completely, enabling the interface to be adapted to a wide range of clocks.
29.5.3 Master Transmitter Mode
After the master initiates a Start condition when writing into the Transmit Holding Register, TWI_THR, it sends a 7-bit
slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following
the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in TWI_MMR).
The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th pulse),
the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The
master polls the data line during this clock pulse and sets the Not Acknowledge bit (NACK) in the status register if the
slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the
interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data written in the TWI_THR, is then shifted
in the internal shifter and transferred. When an acknowledge is detected, the TXRDY bit is set until a new write in the
TWI_THR. When no more data is written into the TWI_THR, the master generates a stop condition to end the transfer.
The end of the complete transfer is marked by the TWI_TXCOMP bit set to one. See Figure 29-5, Figure 29-6, and
Figure 29-7.
SAM7X Series [DATASHEET]
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